configs: Migrate CONFIG_SYS_MAX_FLASH_BANKS to Kconfig

[platform/kernel/u-boot.git] / include / configs / km / pg-wcom-ls102xa.h

diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h
index 69fac2b..9d7a9e1 100644 (file)
--- a/include/configs/km/pg-wcom-ls102xa.h
+++ b/include/configs/km/pg-wcom-ls102xa.h
@@ -6,18 +6,9 @@
 #ifndef __CONFIG_PG_WCOM_LS102XA_H
 #define __CONFIG_PG_WCOM_LS102XA_H
 
-#define CONFIG_SYS_FSL_CLK
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
 /* include common defines/options for all Keymile boards */
 #include "keymile-common.h"
 
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
-
 #define CONFIG_SYS_INIT_RAM_ADDR       OCRAM_BASE_ADDR
 #define CONFIG_SYS_INIT_RAM_SIZE       OCRAM_SIZE
 
@@ -25,8 +16,6 @@
                                          CONFIG_KM_PHRAM + \
                                          CONFIG_KM_RESERVED_PRAM) >> 10)
 
-#define CONFIG_SYS_CLK_FREQ            66666666
-
 #define PHYS_SDRAM                     0x80000000
 #define PHYS_SDRAM_SIZE                        (1u * 1024 * 1024 * 1024)
 
@@ -36,8 +25,6 @@
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
 #define CONFIG_CHIP_SELECTS_PER_CTRL   4
 
-#define CONFIG_DDR_SPD
-
 #define CONFIG_SYS_SPD_BUS_NUM         0
 #define SPD_EEPROM_ADDRESS             0x54
 
@@ -49,7 +36,6 @@
  * IFC Definitions
  */
 /* NOR Flash Definitions */
-#define CONFIG_FSL_IFC
 #define CONFIG_SYS_FLASH_BASE          0x60000000
 #define CONFIG_SYS_FLASH_BASE_PHYS     CONFIG_SYS_FLASH_BASE
 
@@ -82,7 +68,6 @@
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45      /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_MAX_FLASH_BANKS     1       /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      512     /* sectors per device */
 #define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
@@ -103,7 +88,6 @@
 #define CONFIG_SYS_CS0_FTIM3           CONFIG_SYS_NOR_FTIM3
 
 /* NAND Flash Definitions */
-#define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_NAND_BASE           0x68000000
 #define CONFIG_SYS_NAND_BASE_PHYS      CONFIG_SYS_NAND_BASE
 
@@ -124,8 +108,6 @@
                                        | CSOR_NAND_TRHZ_40 \
                                        | CSOR_NAND_BCTLD)
 
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
 #define CONFIG_SYS_NAND_FTIM0          (FTIM0_NAND_TCCST(0x3) | \
                                        FTIM0_NAND_TWP(0x8) | \
                                        FTIM0_NAND_TWCHT(0x3) | \
@@ -150,7 +132,6 @@
 
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_NAND_BLOCK_SIZE     (128 * 1024)
 
 /* QRIO FPGA Definitions */
 #define CONFIG_SYS_QRIO_BASE           0x70000000
@@ -216,8 +197,6 @@
  * Miscellaneous configurable options
  */
 
-#define CONFIG_SYS_LOAD_ADDR           0x82000000
-
 #define CONFIG_LS102XA_STREAM_ID
 
 #define CONFIG_SYS_INIT_SP_OFFSET \
@@ -227,7 +206,6 @@
 
 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 #define CONFIG_SYS_MONITOR_LEN         0x100000     /* 1Mbyte */
-#define CONFIG_SYS_QE_FW_ADDR          0x60020000
 
 #define CONFIG_SYS_BOOTCOUNT_BE