/* High Level Configuration Options */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-#define CONFIG_MP /* support multiple processors */
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_SYS_DPAA_RMAN /* RMan */
/* Environment in SPI Flash */
-#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 20000000
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
#define CONFIG_MISC_INIT_F
-#define CONFIG_MISC_INIT_R
#define CONFIG_HWCONFIG
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */
#define CONFIG_SF_DEFAULT_SPEED 20000000
#define CONFIG_SF_DEFAULT_MODE 0
#define CONFIG_FMAN_ENET
#define CONFIG_PHYLIB_10G
-#define CONFIG_PHY_MARVELL /* there is a marvell phy */
#define CONFIG_PCI_INDIRECT_BRIDGE
*/
/* we don't need flash support */
-#undef CONFIG_FLASH_CFI_MTD
#undef CONFIG_JFFS2_CMDLINE
/*