configs: Finish migration of PHY_GIGE

[platform/kernel/u-boot.git] / include / configs / km / kmp204x-common.h

diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h
index a32c8ba..be4a2d0 100644 (file)
--- a/include/configs/km/kmp204x-common.h
+++ b/include/configs/km/kmp204x-common.h
@@ -8,9 +8,6 @@
 #ifndef _CONFIG_KMP204X_H
 #define _CONFIG_KMP204X_H
 
-#define CONFIG_PHYS_64BIT
-#define CONFIG_PPC_P2041
-
 #define CONFIG_SYS_TEXT_BASE   0xfff40000
 
 #define CONFIG_KM_DEF_NETDEV   "netdev=eth0\0"
@@ -21,8 +18,6 @@
 
 #define CONFIG_NAND_ECC_BCH
 
-#define CONFIG_DISPLAY_BOARDINFO
-
 /* common KM defines */
 #include "keymile-common.h"
 
@@ -34,29 +29,21 @@
 #define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
 
 /* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500                    /* BOOKE e500 family */
-#define CONFIG_E500MC                  /* BOOKE e500mc family */
 #define CONFIG_SYS_BOOK3E_HV           /* Category E.HV supported */
 #define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_MP                      /* support multiple processors */
 
 #define CONFIG_SYS_FSL_CPC             /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC             CONFIG_NUM_DDR_CONTROLLERS
-#define CONFIG_FSL_ELBC                        /* Has Enhanced localbus controller */
-#define CONFIG_PCI                     /* Enable PCI/PCIE */
-#define CONFIG_PCIE1                   /* PCIE controler 1 */
-#define CONFIG_PCIE3                   /* PCIE controler 3 */
+#define CONFIG_SYS_NUM_CPC             CONFIG_SYS_NUM_DDR_CTLRS
+#define CONFIG_PCIE1                   /* PCIE controller 1 */
+#define CONFIG_PCIE3                   /* PCIE controller 3 */
 #define CONFIG_FSL_PCI_INIT            /* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT           /* enable 64-bit PCI resources */
 
 #define CONFIG_SYS_DPAA_RMAN           /* RMan */
 
-#define CONFIG_FSL_LAW                 /* Use common FSL init code */
-
 /* Environment in SPI Flash */
 #define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_SPI_BUS              0
 #define CONFIG_ENV_SPI_CS               0
 #define CONFIG_ENV_SPI_MAX_HZ           20000000
@@ -112,7 +99,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_CHIP_SELECTS_PER_CTRL   (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
 #define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR3
 #define CONFIG_FSL_DDR_INTERACTIVE
 
 #define CONFIG_SYS_SPD_BUS_NUM 0
@@ -166,7 +152,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 
 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
-#define CONFIG_CMD_NAND
 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 
 #define CONFIG_BCH
@@ -211,7 +196,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_BOOTCOUNT_LIMIT
 #define CONFIG_SYS_BOOTCOUNT_ADDR      (CONFIG_SYS_QRIO_BASE + 0x20)
 
-#define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_EARLY_INIT_R      /* call board_early_init_r function */
 #define CONFIG_MISC_INIT_F
 #define CONFIG_MISC_INIT_R
@@ -255,18 +239,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 
 #define CONFIG_KM_CONSOLE_TTY  "ttyS0"
 
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE     /* enable fit_format_{error,warning}() */
-
 /* I2C */
 
 #define CONFIG_SYS_I2C
@@ -296,11 +268,7 @@ int get_scl(void);
 /*
  * eSPI - Enhanced SPI
  */
-#define CONFIG_FSL_ESPI
 #define CONFIG_SPI_FLASH_BAR   /* 4 byte-addressing */
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED         20000000
 #define CONFIG_SF_DEFAULT_MODE          0
 
@@ -372,17 +340,13 @@ int get_scl(void);
 #define CONFIG_PHY_MARVELL             /* there is a marvell phy */
 
 #define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_PNP                 /* do pci plug-and-play */
 
 #define CONFIG_PCI_SCAN_SHOW           /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
 
 /* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11
 #define CONFIG_SYS_TBIPA_VALUE 8
-#define CONFIG_PHYLIB          /* recommended PHY management */
 #define CONFIG_ETHPRIME                "FM1@DTSEC5"
-#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
 
 /*
  * Environment
@@ -402,10 +366,8 @@ int get_scl(void);
  * additionnal command line configuration.
  */
 #define CONFIG_CMD_PCI
-#define CONFIG_CMD_ERRATA
 
 /* we don't need flash support */
-#define CONFIG_SYS_NO_FLASH
 #undef CONFIG_FLASH_CFI_MTD
 #undef CONFIG_JFFS2_CMDLINE
 
@@ -422,6 +384,7 @@ int get_scl(void);
 #endif
 
 #define __USB_PHY_TYPE utmi
+#define CONFIG_USB_EHCI_FSL
 
 /*
  * Environment Configuration