Merge branch 'master' of http://git.denx.de/u-boot-mmc

[platform/kernel/u-boot.git] / include / configs / km / km8321-common.h

diff --git a/include/configs/km/km8321-common.h b/include/configs/km/km8321-common.h
index 6fab45e..5bc546c 100644 (file)
--- a/include/configs/km/km8321-common.h
+++ b/include/configs/km/km8321-common.h
@@ -17,10 +17,7 @@
  * (C) Copyright 2010-2011
  * Thomas Reufer, KEYMILE Ltd, thomas.reufer@keymile.com
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __CONFIG_KM8321_COMMON_H
@@ -33,14 +30,11 @@
 #define CONFIG_MPC832x /* MPC832x CPU specific */
 #define CONFIG_KM8321  /* Keymile PBEC8321 board specific */
 
-#define CONFIG_KM_DEF_ROOTPATH         \
-       "rootpath=/opt/eldk/ppc_8xx\0"
+#define CONFIG_KM_DEF_ARCH     "arch=ppc_8xx\0"
 
 /* include common defines/options for all 83xx Keymile boards */
 #include "km83xx-common.h"
 
-#define CONFIG_MISC_INIT_R
-
 /*
  * System IO Config
  */
@@ -68,10 +62,17 @@
        HRCWH_BIG_ENDIAN | \
        HRCWH_LALE_NORMAL)
 
+#define CONFIG_SYS_DDRCDR (\
+       DDRCDR_EN | \
+       DDRCDR_PZ_MAXZ | \
+       DDRCDR_NZ_MAXZ | \
+       DDRCDR_M_ODR)
+
 #define CONFIG_SYS_DDR_CS0_BNDS                0x0000007f
 #define CONFIG_SYS_DDR_SDRAM_CFG       (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
                                         SDRAM_CFG_32_BE | \
-                                        SDRAM_CFG_SREN)
+                                        SDRAM_CFG_SREN | \
+                                        SDRAM_CFG_HSE)
 
 #define CONFIG_SYS_DDR_SDRAM_CFG2      0x00401000
 #define CONFIG_SYS_DDR_CLK_CNTL                (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
@@ -83,7 +84,7 @@
                                         CSCONFIG_ROW_BIT_13 | \
                                         CSCONFIG_COL_BIT_10)
 
-#define CONFIG_SYS_DDR_MODE    0x47860252
+#define CONFIG_SYS_DDR_MODE    0x47860242
 #define CONFIG_SYS_DDR_MODE2   0x8080c000
 
 #define CONFIG_SYS_DDR_TIMING_0        ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
@@ -95,27 +96,27 @@
                                 (0 << TIMING_CFG0_WRT_SHIFT) | \
                                 (0 << TIMING_CFG0_RWT_SHIFT))
 
-#define CONFIG_SYS_DDR_TIMING_1        ((TIMING_CFG1_CASLAT_50) | \
+#define CONFIG_SYS_DDR_TIMING_1        ((TIMING_CFG1_CASLAT_40) | \
                                 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
                                 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
-                                (2 << TIMING_CFG1_WRREC_SHIFT) | \
-                                (6 << TIMING_CFG1_REFREC_SHIFT) | \
-                                (2 << TIMING_CFG1_ACTTORW_SHIFT) | \
-                                (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
-                                (2 << TIMING_CFG1_PRETOACT_SHIFT))
+                                (3 << TIMING_CFG1_WRREC_SHIFT) | \
+                                (7 << TIMING_CFG1_REFREC_SHIFT) | \
+                                (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+                                (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+                                (3 << TIMING_CFG1_PRETOACT_SHIFT))
 
 #define CONFIG_SYS_DDR_TIMING_2        ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
                                 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
                                 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
                                 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
-                                (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+                                (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
                                 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
                                 (5 << TIMING_CFG2_CPO_SHIFT))
 
 #define CONFIG_SYS_DDR_TIMING_3        0x00000000
 
 #define CONFIG_SYS_KMBEC_FPGA_BASE     0xE8000000
-#define        CONFIG_SYS_KMBEC_FPGA_SIZE      128
+#define CONFIG_SYS_KMBEC_FPGA_SIZE     128
 
 /* EEprom support */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
@@ -123,7 +124,10 @@
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CONFIG_SYS_LCRR                (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2)
+#define CONFIG_SYS_LCRR_DBYP   0x80000000
+#define CONFIG_SYS_LCRR_EADC   0x00010000
+#define CONFIG_SYS_LCRR_CLKDIV 0x00000002
+
 #define CONFIG_SYS_LBC_LBCR    0x00000000
 
 /*