Convert CONFIG_SYS_SPL_MALLOC_SIZE et al to Kconfig

[platform/kernel/u-boot.git] / include / configs / j721e_evm.h

diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index e4b167d..a814961 100644 (file)
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -20,44 +20,13 @@
 
 /* SPL Loader Configuration */
 #if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
-#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SPL_TEXT_BASE +        \
-                                        CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE)
 #define CONFIG_SYS_UBOOT_BASE          0x50280000
 /* Image load address in RAM for DFU boot*/
 #else
 #define CONFIG_SYS_UBOOT_BASE          0x50080000
-/*
- * Maximum size in memory allocated to the SPL BSS. Keep it as tight as
- * possible (to allow the build to go through), as this directly affects
- * our memory footprint. The less we use for BSS the more we have available
- * for everything else.
- */
-#define CONFIG_SPL_BSS_MAX_SIZE                0xA000
-/*
- * Link BSS to be within SPL in a dedicated region located near the top of
- * the MCU SRAM, this way making it available also before relocation. Note
- * that we are not using the actual top of the MCU SRAM as there is a memory
- * location filled in by the boot ROM that we want to read out without any
- * interference from the C context.
- */
-#define CONFIG_SPL_BSS_START_ADDR      (CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\
-                                        CONFIG_SPL_BSS_MAX_SIZE)
-/* Set the stack right below the SPL BSS section */
-#define CONFIG_SYS_INIT_SP_ADDR         CONFIG_SPL_BSS_START_ADDR
-/* Configure R5 SPL post-relocation malloc pool in DDR */
-#define CONFIG_SYS_SPL_MALLOC_START    0x84000000
-#define CONFIG_SYS_SPL_MALLOC_SIZE     SZ_16M
-/* Image load address in RAM for DFU boot*/
 #endif
 
-#ifdef CONFIG_SYS_K3_SPL_ATF
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME        "tispl.bin"
-#endif
-
-#define CONFIG_SPL_MAX_SIZE            CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
-
 #define CONFIG_SYS_BOOTM_LEN           SZ_64M
-#define CONFIG_CQSPI_REF_CLK           133333333
 
 /* HyperFlash related configuration */
 
@@ -122,9 +91,8 @@
        "partitions=" PARTS_DEFAULT
 
 /* Set the default list of remote processors to boot */
-#if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
+#if defined(CONFIG_TARGET_J7200_A72_EVM)
 #define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY                         \
-       "dorprocboot=1\0"                                               \
        "do_main_cpsw0_qsgmii_phyinit=1\0"                              \
        "init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;"               \
                 "gpio clear gpio@22_16\0"                              \
@@ -136,6 +104,22 @@
 #ifdef DEFAULT_RPROCS
 #undef DEFAULT_RPROCS
 #endif
+#elif defined(CONFIG_TARGET_J721E_A72_EVM)
+#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY                         \
+       "init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;"               \
+                "gpio clear gpio@22_16\0"                              \
+       "main_cpsw0_qsgmii_phyinit="                                    \
+       "if test $board_name = J721EX-PM1-SOM || test $board_name = J721EX-PM2-SOM " \
+       "|| test $board_name = j721e; then " \
+       "do_main_cpsw0_qsgmii_phyinit=1; else "                 \
+       "do_main_cpsw0_qsgmii_phyinit=0; fi;"                   \
+       "if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot} -eq 1 && " \
+                       "test ${boot} = mmc; then "                     \
+               "run init_main_cpsw0_qsgmii_phy;"                       \
+       "fi;\0"
+#ifdef DEFAULT_RPROCS
+#undef DEFAULT_RPROCS
+#endif
 #endif
 
 #ifdef CONFIG_TARGET_J721E_A72_EVM