powerpc/corenet_ds: Move CONFIG_SYS_TEXT_BASE into corenet_ds.h

[platform/kernel/u-boot.git] / include / configs / ip04.h

diff --git a/include/configs/ip04.h b/include/configs/ip04.h
index 425a745..528363c 100644 (file)
--- a/include/configs/ip04.h
+++ b/include/configs/ip04.h
@@ -20,7 +20,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf532-0.5
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_NAND
 
 
@@ -116,7 +115,6 @@
 
 #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
 #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
-#define BFIN_NAND_READY     PF10
 #define BFIN_NAND_WRITE(addr, cmd) \
        do { \
                bfin_write8(addr, cmd); \
@@ -125,14 +123,7 @@
 
 #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_DEV_READY(chip)      (bfin_read_FIO_FLAG_D() & BFIN_NAND_READY)
-#define NAND_PLAT_INIT() \
-       do { \
-               bfin_write_FIO_DIR(bfin_read_FIO_DIR() & ~BFIN_NAND_READY); \
-               bfin_write_FIO_INEN(bfin_read_FIO_INEN() | BFIN_NAND_READY); \
-               bfin_write_FIO_EDGE(bfin_read_FIO_EDGE() & ~BFIN_NAND_READY); \
-               bfin_write_FIO_POLAR(bfin_read_FIO_POLAR() & ~BFIN_NAND_READY); \
-       } while (0)
+#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF10
 
 
 /*