* by Stefan Roese, DENX Software Engineering, sr@denx.de.
* and Grant Erickson <gerickson@nuovations.com>
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+
*/
/************************************************************************
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_IO64 1 /* Board is Io64 */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_405EX 1 /* Specifc 405EX support*/
#define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */
#define CONFIG_MISC_INIT_R
#define CONFIG_LAST_STAGE_INIT
-#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
-#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
-#define CONFIG_AUTOBOOT_STOP_STR " "
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE
-
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#define CONFIG_PCA9698 1 /* NXP PCA9698 */
#define CONFIG_SYS_FPGA_COUNT 2
+#define CONFIG_SYS_FPGA_PTR { \
+ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
+ (struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
+
+#define CONFIG_SYS_FPGA_COMMON
+
#define CONFIG_SYS_LATCH0_RESET 0xffff
#define CONFIG_SYS_LATCH0_BOOT 0xffff
#define CONFIG_SYS_LATCH1_RESET 0xffbf