#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_INTEGRATOR
+#define CONFIG_ARCH_INTEGRATOR
/*
* High Level Configuration Options
* (easy to change)
*/
-#define CFG_MEMTEST_START 0x100000
-#define CFG_MEMTEST_END 0x10000000
-#define CFG_HZ 1000
-#define CFG_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */
-#define CFG_TIMERBASE 0x13000100
+#define CONFIG_SYS_MEMTEST_START 0x100000
+#define CONFIG_SYS_MEMTEST_END 0x10000000
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */
+#define CONFIG_SYS_TIMERBASE 0x13000100
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
/*
* Size of malloc() pool
*/
-#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
/*
* Hardware drivers
*/
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC91111
#define CONFIG_SMC_USE_32_BIT
#define CONFIG_SMC91111_BASE 0xC8000000
#undef CONFIG_SMC91111_EXT_PHY
/*
* NS16550 Configuration
*/
-#define CFG_PL011_SERIAL
+#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK 14745600
-#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 }
+#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, (void *)CONFIG_SYS_SERIAL1 }
#define CONFIG_CONS_INDEX 0
#define CONFIG_BAUDRATE 38400
-#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CFG_SERIAL0 0x16000000
-#define CFG_SERIAL1 0x17000000
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_SERIAL0 0x16000000
+#define CONFIG_SYS_SERIAL1 0x17000000
+
/*
-#define CONFIG_COMMANDS (CFG_CMD_DFL | CFG_CMD_PCI)
-*/
-#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | \
- CFG_CMD_BDI | CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_ENV \
- )
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-/* #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+
#if 0
#define CONFIG_BOOTDELAY 2
-#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0"
+#define CONFIG_BOOTARGS "root=/dev/nfs nfsroot=<IP address>:/<exported rootfs> mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
#define CONFIG_BOOTCOMMAND "bootp ; bootm"
#endif
+/* The kernel command line & boot command below are for a platform flashed with afu.axf
+
+Image 666 Block 0 End Block 0 address 0x24000000 exec 0x24000000- name u-boot
+Image 667 Block 1 End Block 13 address 0x24040000 exec 0x24040000- name u-linux
+Image 668 Block 14 End Block 33 address 0x24380000 exec 0x24380000- name rootfs
+SIB at Block62 End Block62 address 0x24f80000
-/* Flash loaded
- - U-Boot
- - u-linux
- - system.cramfs
*/
#define CONFIG_BOOTDELAY 2
-#define CONFIG_BOOTARGS "root=/dev/mtdblock2 mem=128M ip=dhcp netdev=27,0, \
-0xfc800000,0xfc800010,eth0 video=clcdfb:0"
-#define CONFIG_BOOTCOMMAND "cp 0x24040000 0x7fc0 0x80000; bootm"
+#define CONFIG_BOOTARGS "root=/dev/mtdblock2 mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0 console=ttyAMA0"
+#define CONFIG_BOOTCOMMAND "cp 0x24080000 0x7fc0 0x100000; bootm"
/*
* Miscellaneous configurable options
*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "Integrator-CP # " /* Monitor Command Prompt */
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "Integrator-CP # " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/
/* Print Buffer Size */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size*/
-#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
-#define CFG_LOAD_ADDR 0x7fc0 /* default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */
/*-----------------------------------------------------------------------
* Stack sizes
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* FLASH and environment organization
+
+ * Top varies according to amount fitted
+ * Reserve top 4 blocks of flash
+ * - ARM Boot Monitor
+ * - Unused
+ * - SIB block
+ * - U-Boot environment
+ *
+ * Base is always 0x24000000
+
*/
-#define CFG_FLASH_BASE 0x24000000
-#define CFG_MAX_FLASH_SECT 64
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */
-#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_BASE 0x24000000
+#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_MAX_FLASH_SECT 64
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */
+#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-#define CFG_MONITOR_BASE 0x24F40000
-#define CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_ADDR 0x24F00000
-#define CFG_ENV_SECT_SIZE 0x40000 /* 256KB */
-#define CFG_ENV_SIZE 8192 /* 8KB */
+#define CONFIG_SYS_MONITOR_LEN 0x00100000
+#define CONFIG_ENV_IS_IN_FLASH 1
+
+/*
+ * Move up the U-Boot & monitor area if more flash is fitted.
+ * If this U-Boot is to be run on Integrators with varying flash sizes,
+ * drivers/mtd/cfi_flash.c::flash_init() can read the Integrator CP_FLASHPROG
+ * register and dynamically assign CONFIG_ENV_ADDR & CONFIG_SYS_MONITOR_BASE
+ * - CONFIG_SYS_MONITOR_BASE is set to indicate that the environment is not
+ * embedded in the boot monitor(s) area
+ */
+#if ( PHYS_FLASH_SIZE == 0x04000000 )
+
+#define CONFIG_ENV_ADDR 0x27F00000
+#define CONFIG_SYS_MONITOR_BASE 0x27F40000
+
+#elif (PHYS_FLASH_SIZE == 0x02000000 )
+
+#define CONFIG_ENV_ADDR 0x25F00000
+#define CONFIG_SYS_MONITOR_BASE 0x25F40000
+
+#else
+
+#define CONFIG_ENV_ADDR 0x24F00000
+#define CONFIG_SYS_MONITOR_BASE 0x27F40000
+
+#endif
+#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */
+#define CONFIG_ENV_SIZE 8192 /* 8KB */
+/*-----------------------------------------------------------------------
+ * CP control registers
+ */
+#define CPCR_BASE 0xCB000000 /* CP Registers*/
+#define OS_FLASHPROG 0x00000004 /* Flash register*/
+#define CPMASK_EXTRABANK 0x8
+#define CPMASK_FLASHSIZE 0x4
+#define CPMASK_FLWREN 0x2
+#define CPMASK_FLVPPEN 0x1
+
+/*
+ * The ARM boot monitor initializes the board.
+ * However, the default U-Boot code also performs the initialization.
+ * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT
+ * - see documentation supplied with board for details of how to choose the
+ * image to run at reset/power up
+ * e.g. whether the ARM Boot Monitor runs before U-Boot
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+ */
+
+/*
+ * The ARM boot monitor does not relocate U-Boot.
+ * However, the default U-Boot code performs the relocation check,
+ * and may relocate the code if the memory map is changed.
+ * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT
+
+#define SKIP_CONFIG_RELOCATE_UBOOT
+
+ */
/*-----------------------------------------------------------------------
* There are various dependencies on the core module (CM) fitted
* Users should refer to their CM user guide
* - when porting adjust u-boot/Makefile accordingly
- * to define the necessary CONFIG_ s for the CM involved
- * see e.g. integratorcp_CM926EJ-S_config
- */
-
-#define CM_BASE 0x10000000
-
-/* CM registers common to all integrator/CP CMs */
-#define OS_CTRL 0x0000000C
-#define CMMASK_REMAP 0x00000005 /* set remap & led */
-#define CMMASK_RESET 0x00000008
-#define OS_LOCK 0x00000014
-#define CMVAL_LOCK 0x0000A000 /* locking value */
-#define CMMASK_LOCK 0x0000005F /* locking value */
-#define CMVAL_UNLOCK 0x00000000 /* any value != CM_LOCKVAL */
-#define OS_SDRAM 0x00000020
-#define OS_INIT 0x00000024
-#define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */
-#define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */
-#define CMMASK_LOWVEC 0x00000004 /* vectors @ 0x00000000 */
-#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
-#define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual
- * - PLL test clock bypassed
- * - bus clock ratio 2
- * - little endian
- * - vectors at zero
- */
-#endif /* CM1022xx */
-
-#define CMMASK_LE 0x00000008 /* little endian */
-#define CMMASK_CMxx6_COMMON 0x00000100 /* Common value for CMxx6
- * - divisor/ratio b00000001
- * bx
- * - HCLKDIV b000
- * bxx
- * - PLL BYPASS b00
- */
-
-/* Determine CM characteristics */
-
-#undef CONFIG_CM_MULTIPLE_SSRAM
-#undef CONFIG_CM_SPD_DETECT
-#undef CONFIG_CM_REMAP
-#undef CONFIG_CM_INIT
-#undef CONFIG_CM_TCRAM
-
-#if defined (CONFIG_CM946E_S) || defined (CONFIG_CM966E_S)
-#define CONFIG_CM_MULTIPLE_SSRAM /* CM has multiple SSRAM mapping */
-#endif
+ * to define the necessary CONFIG_ s for the CM involved
+ * see e.g. cp_926ejs_config
+ */
+
+#include "armcoremodule.h"
-#ifndef CONFIG_CM922t_XA10
-#define CONFIG_CM_SPD_DETECT /* CM supports SPD query */
-#define OS_SPD 0x00000100 /* Address of SPD data */
-#define CONFIG_CM_REMAP /* CM supports remapping */
-#define CONFIG_CM_INIT /* CM has initialization reg */
-#endif
-
-#if defined(CONFIG_CM926EJ_S) || defined (CONFIG_CM946E_S) || \
- defined(CONFIG_CM966E_S) || defined (CONFIG_CM1026EJ_S) || \
- defined(CONFIG_CM1136JF_S)
-#define CONFIG_CM_TCRAM /* CM has TCRAM */
-#endif
+/*
+ * If CONFIG_SKIP_LOWLEVEL_INIT is not defined &
+ * the core module has a CM_INIT register
+ * then the U-Boot initialisation code will
+ * e.g. ARM Boot Monitor or pre-loader is repeated once
+ * (to re-initialise any existing CM_INIT settings to safe values).
+ *
+ * This is usually not the desired behaviour since the platform
+ * will either reboot into the ARM monitor (or pre-loader)
+ * or continuously cycle thru it without U-Boot running,
+ * depending upon the setting of Integrator/CP switch S2-4.
+ *
+ * However it may be needed if Integrator/CP switch S2-1
+ * is set OFF to boot direct into U-Boot.
+ * In that case comment out the line below.
+#undef CONFIG_CM_INIT
+ */
#endif /* __CONFIG_H */
projects / platform / kernel / u-boot.git / blobdiff