Convert CONFIG_SPL_PAD_TO et al to Kconfig

[platform/kernel/u-boot.git] / include / configs / imx8mq_evk.h

diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
index 8fff3bf..8d8bdb8 100644 (file)
--- a/include/configs/imx8mq_evk.h
+++ b/include/configs/imx8mq_evk.h
@@ -12,7 +12,6 @@
 
 #define CONFIG_SYS_BOOTM_LEN           (64 * SZ_1M)
 
-#define CONFIG_SPL_MAX_SIZE            (124 * 1024)
 #define CONFIG_SYS_MONITOR_LEN         (512 * 1024)
 
 #ifdef CONFIG_SPL_BUILD
@@ -29,8 +28,6 @@
 /* For RAW image gives a error info not panic */
 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
 
-#undef CONFIG_DM_MMC
-
 #define CONFIG_POWER_PFUZE100
 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
 #endif
@@ -39,9 +36,6 @@
 /* ENET1 */
 #if defined(CONFIG_CMD_NET)
 #define CONFIG_FEC_MXC_PHYADDR          0
-#define FEC_QUIRK_ENET_MAC
-
-#define IMX_FEC_BASE                   0x30BE0000
 #endif
 
 #ifndef CONFIG_SPL_BUILD
@@ -66,7 +60,7 @@
        "initrd_addr=0x43800000\0"              \
        "bootm_size=0x10000000\0" \
        "mmcpart=1\0" \
-       "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+       "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
 
 /* Link Definitions */
 
@@ -77,20 +71,12 @@
 #define CONFIG_SYS_INIT_SP_ADDR \
        (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
-#define CONFIG_MMCROOT                 "/dev/mmcblk1p2"  /* USDHC2 */
 
 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 #define PHYS_SDRAM                      0x40000000
 #define PHYS_SDRAM_SIZE                        0xC0000000 /* 3GB DDR */
 
-#define CONFIG_MXC_UART_BASE           UART1_BASE_ADDR
-
-/* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE              1024
-#define CONFIG_SYS_MAXARGS             64
-#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \
-                                       sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_MXC_UART_BASE           UART_BASE_ADDR(1)
 
 #define CONFIG_SYS_FSL_USDHC_NUM       2
 #define CONFIG_SYS_FSL_ESDHC_ADDR       0