global: Migrate CONFIG_MXC_UART_BASE to CFG
[platform/kernel/u-boot.git] / include / configs / imx8mp_rsb3720.h
index c0f2824..495ca31 100644 (file)
 #include <asm/arch/imx-regs.h>
 #include <config_distro_bootcmd.h>
 
-#define CONFIG_SYS_BOOTM_LEN           (32 * SZ_1M)
-
-#define CONFIG_SPL_MAX_SIZE            (152 * 1024)
-#define CONFIG_SYS_MONITOR_LEN         (512 * 1024)
-#define CONFIG_SYS_UBOOT_BASE  (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+#define CFG_SYS_UBOOT_BASE     (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
 /* GUIDs for capsule updatable firmware images */
 #define IMX8MP_RSB3720A1_4G_FIT_IMAGE_GUID \
                 0x5f, 0xd3, 0x6b, 0x9b, 0xe5, 0xb9)
 
 #ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_STACK               0x960000
-#define CONFIG_SPL_BSS_START_ADDR      0x0098FC00
-#define CONFIG_SPL_BSS_MAX_SIZE                0x400   /* 1 KB */
-#define CONFIG_SYS_SPL_MALLOC_START    0x42200000
-#define CONFIG_SYS_SPL_MALLOC_SIZE     SZ_512K /* 512 KB */
-
-#define CONFIG_MALLOC_F_ADDR           0x184000 /* malloc f used before \
+#define CFG_MALLOC_F_ADDR              0x184000 /* malloc f used before \
                                                  * GD_FLG_FULL_MALLOC_INIT \
                                                  * set \
                                                  */
 
-#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
 
 #if defined(CONFIG_NAND_BOOT)
 #define CONFIG_SPL_NAND_MXS
 /* ENET Config */
 /* ENET1 */
 #if defined(CONFIG_CMD_NET)
-#define CONFIG_FEC_MXC_PHYADDR          4
-#define FEC_QUIRK_ENET_MAC
-
-#define DWC_NET_PHYADDR                        4
-#ifdef CONFIG_DWC_ETH_QOS
-#define CONFIG_SYS_NONCACHED_MEMORY     (1 * SZ_1M)     /* 1M */
-#endif
+#define CFG_FEC_MXC_PHYADDR          4
 
 #define PHY_ANEG_TIMEOUT 20000
 
@@ -88,7 +71,7 @@
        BOOT_TARGET_DHCP(func)
 
 /* Initial environment variables */
-#define CONFIG_EXTRA_ENV_SETTINGS              \
+#define CFG_EXTRA_ENV_SETTINGS         \
        BOOTENV \
        "script=boot.scr\0" \
        "image=Image\0" \
                "fi;\0"
 
 /* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR       0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE       0x80000
-#define CONFIG_SYS_INIT_SP_OFFSET \
-       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
-       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+#define CFG_SYS_INIT_RAM_ADDR  0x40000000
+#define CFG_SYS_INIT_RAM_SIZE  0x80000
 
 
 /* Totally 6GB or 4G DDR */
-#define CONFIG_SYS_SDRAM_BASE          0x40000000
+#define CFG_SYS_SDRAM_BASE             0x40000000
 #define PHYS_SDRAM                     0x40000000
 #if defined(CONFIG_TARGET_IMX8MP_RSB3720A1_6G)
 #define PHYS_SDRAM_SIZE                        0xC0000000      /* 3 GB */
 #define PHYS_SDRAM_2_SIZE              0x80000000      /* 2 GB */
 #endif
 
-#define CONFIG_MXC_UART_BASE           UART_BASE_ADDR(3)
-
-/* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE              2048
-#define CONFIG_SYS_MAXARGS             64
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \
-                                       sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CFG_MXC_UART_BASE              UART3_BASE_ADDR
 
-#define CONFIG_SYS_FSL_USDHC_NUM       2
-#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+#define CFG_SYS_FSL_USDHC_NUM  2
+#define CFG_SYS_FSL_ESDHC_ADDR 0
 
 #ifdef CONFIG_FSL_FSPI
 #define FSL_FSPI_FLASH_SIZE            SZ_32M
 #ifdef CONFIG_NAND_MXS
 
 /* NAND stuff */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
-#define CONFIG_SYS_NAND_BASE           0x20000000
+#define CFG_SYS_NAND_BASE           0x20000000
 #endif /* CONFIG_NAND_MXS */
 
 #endif /* __IMX8MP_RSB3720_H */