global: Migrate CONFIG_MXC_UART_BASE to CFG

[platform/kernel/u-boot.git] / include / configs / imx8mp_rsb3720.h

diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h
index 5be4609..495ca31 100644 (file)
--- a/include/configs/imx8mp_rsb3720.h
+++ b/include/configs/imx8mp_rsb3720.h
@@ -12,7 +12,7 @@
 #include <asm/arch/imx-regs.h>
 #include <config_distro_bootcmd.h>
 
-#define CONFIG_SYS_UBOOT_BASE  (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+#define CFG_SYS_UBOOT_BASE     (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
 /* GUIDs for capsule updatable firmware images */
 #define IMX8MP_RSB3720A1_4G_FIT_IMAGE_GUID \
@@ -24,7 +24,7 @@
                 0x5f, 0xd3, 0x6b, 0x9b, 0xe5, 0xb9)
 
 #ifdef CONFIG_SPL_BUILD
-#define CONFIG_MALLOC_F_ADDR           0x184000 /* malloc f used before \
+#define CFG_MALLOC_F_ADDR              0x184000 /* malloc f used before \
                                                  * GD_FLG_FULL_MALLOC_INIT \
                                                  * set \
                                                  */
@@ -39,7 +39,7 @@
 /* ENET Config */
 /* ENET1 */
 #if defined(CONFIG_CMD_NET)
-#define CONFIG_FEC_MXC_PHYADDR          4
+#define CFG_FEC_MXC_PHYADDR          4
 
 #define PHY_ANEG_TIMEOUT 20000
 
@@ -71,7 +71,7 @@
        BOOT_TARGET_DHCP(func)
 
 /* Initial environment variables */
-#define CONFIG_EXTRA_ENV_SETTINGS              \
+#define CFG_EXTRA_ENV_SETTINGS         \
        BOOTENV \
        "script=boot.scr\0" \
        "image=Image\0" \
@@ -131,12 +131,12 @@
                "fi;\0"
 
 /* Link Definitions */
-#define CONFIG_SYS_INIT_RAM_ADDR       0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE       0x80000
+#define CFG_SYS_INIT_RAM_ADDR  0x40000000
+#define CFG_SYS_INIT_RAM_SIZE  0x80000
 
 
 /* Totally 6GB or 4G DDR */
-#define CONFIG_SYS_SDRAM_BASE          0x40000000
+#define CFG_SYS_SDRAM_BASE             0x40000000
 #define PHYS_SDRAM                     0x40000000
 #if defined(CONFIG_TARGET_IMX8MP_RSB3720A1_6G)
 #define PHYS_SDRAM_SIZE                        0xC0000000      /* 3 GB */
@@ -148,7 +148,7 @@
 #define PHYS_SDRAM_2_SIZE              0x80000000      /* 2 GB */
 #endif
 
-#define CONFIG_MXC_UART_BASE           UART3_BASE_ADDR
+#define CFG_MXC_UART_BASE              UART3_BASE_ADDR
 
 #define CFG_SYS_FSL_USDHC_NUM  2
 #define CFG_SYS_FSL_ESDHC_ADDR 0
@@ -166,7 +166,7 @@
 #ifdef CONFIG_NAND_MXS
 
 /* NAND stuff */
-#define CONFIG_SYS_NAND_BASE           0x20000000
+#define CFG_SYS_NAND_BASE           0x20000000
 #endif /* CONFIG_NAND_MXS */
 
 #endif /* __IMX8MP_RSB3720_H */