#define CONFIG_SPL_MAX_SIZE (152 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x960000
#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00
#define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#undef CONFIG_DM_MMC
-#undef CONFIG_DM_PMIC
-#undef CONFIG_DM_PMIC_PFUZE100
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
#define CONFIG_POWER_PCA9450
-#define CONFIG_SYS_I2C
-
#endif
#if defined(CONFIG_CMD_NET)
-#define CONFIG_ETHPRIME "eth1" /* Set eqos to primary since we use its MDIO */
-
-#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 1
#define FEC_QUIRK_ENET_MAC
#define DWC_NET_PHYADDR 1
-#ifdef CONFIG_DWC_ETH_QOS
-#define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */
-#endif
#define PHY_ANEG_TIMEOUT 20000
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
BOOTENV \
- "scriptaddr=0x43500000\0" \
- "kernel_addr_r=0x40880000\0" \
+ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"image=Image\0" \
"console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
- "fdt_addr=0x43000000\0" \
+ "fdt_addr_r=0x43000000\0" \
"boot_fdt=try\0" \
- "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
"initrd_addr=0x43800000\0" \
"bootm_size=0x10000000\0" \
- "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
/* Link Definitions */
-#define CONFIG_LOADADDR 0x40480000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN SZ_32M
-
/* Totally 6GB DDR */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_FSL_USDHC
-
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
-
-#define CONFIG_SYS_I2C_SPEED 100000
-
#endif