#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
# define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif /* CONFIG_SPL_BUILD */
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
-
#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 2) \
BOOTENV
/* Link Definitions */
-#define CONFIG_SYS_LOAD_ADDR 0x40480000
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN SZ_32M
#define CONFIG_SYS_SDRAM_BASE 0x40000000
/* SDRAM configuration */
#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
#define CONFIG_SYS_BOOTM_LEN SZ_256M
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
-#define CONFIG_SYS_MEMTEST_END \
- (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
-
/* UART */
#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
/* USDHC */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#endif /* __IMX8MM_ICORE_MX8MM_H */