Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

[platform/kernel/u-boot.git] / include / configs / igep00x0.h

diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h
index d8e87c3..43dd06e 100644 (file)
--- a/include/configs/igep00x0.h
+++ b/include/configs/igep00x0.h
@@ -30,6 +30,7 @@
  */
 #define CONFIG_OMAP            1       /* in a TI OMAP core */
 #define CONFIG_OMAP34XX                1       /* which is a 34XX */
+#define CONFIG_OMAP_GPIO
 
 #define CONFIG_SDRC    /* The chip has SDRC controller */
 
@@ -179,7 +180,7 @@
                "bootm ${loadaddr}\0" \
 
 #define CONFIG_BOOTCOMMAND \
-       "if mmc rescan ${mmcdev}; then " \
+       "mmc dev ${mmcdev}; if mmc rescan; then " \
                "echo SD/MMC found on device ${mmcdev};" \
                "if run loadbootenv; then " \
                        "run importbootenv;" \
@@ -230,19 +231,11 @@
 #define CONFIG_SYS_HZ                  1000
 
 /*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE       (128 << 10)     /* regular stack 128 KiB */
-
-/*
  * Physical Memory Map
  *
  */
 #define CONFIG_NR_DRAM_BANKS   2       /* CS1 may or may not be populated */
 #define PHYS_SDRAM_1           OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE      (32 << 20)      /* at least 32 meg */
 #define PHYS_SDRAM_2           OMAP34XX_SDRC_CS1
 
 /*
@@ -287,6 +280,11 @@
 #define CONFIG_SMC911X_BASE    0x2C000000
 #endif /* (CONFIG_CMD_NET) */
 
+/*
+ * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
+ * and older u-boot.bin with the new U-Boot SPL.
+ */
+#define CONFIG_SYS_TEXT_BASE           0x80008000
 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
 #define CONFIG_SYS_INIT_RAM_ADDR       0x4020f800
 #define CONFIG_SYS_INIT_RAM_SIZE       0x800
@@ -294,4 +292,68 @@
                                         CONFIG_SYS_INIT_RAM_SIZE - \
                                         GENERATED_GBL_DATA_SIZE)
 
+/* SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_TEXT_BASE           0x40200800
+#define CONFIG_SPL_MAX_SIZE            (54 * 1024)
+#define CONFIG_SPL_STACK               LOW_LEVEL_SRAM_STACK
+
+/* move malloc and bss high to prevent clashing with the main image */
+#define CONFIG_SYS_SPL_MALLOC_START    0x87000000
+#define CONFIG_SYS_SPL_MALLOC_SIZE     0x80000
+#define CONFIG_SPL_BSS_START_ADDR      0x87080000      /* end of minimum RAM */
+#define CONFIG_SPL_BSS_MAX_SIZE                0x80000         /* 512 KB */
+
+/* MMC boot config */
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR        0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS     0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION   1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME       "u-boot.img"
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_LDSCRIPT            "$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+#ifdef CONFIG_BOOT_ONENAND
+#define CONFIG_SPL_ONENAND_SUPPORT
+
+/* OneNAND boot config */
+#define CONFIG_SYS_ONENAND_U_BOOT_OFFS  0x80000
+#define CONFIG_SYS_ONENAND_PAGE_SIZE   2048
+#define CONFIG_SPL_ONENAND_LOAD_ADDR    0x80000
+#define CONFIG_SPL_ONENAND_LOAD_SIZE    \
+       (512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR)
+
+#endif
+
+#ifdef CONFIG_BOOT_NAND
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT     64
+#define CONFIG_SYS_NAND_PAGE_SIZE      2048
+#define CONFIG_SYS_NAND_OOBSIZE                64
+#define CONFIG_SYS_NAND_BLOCK_SIZE     (128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS  0
+#define CONFIG_SYS_NAND_ECCPOS         {2, 3, 4, 5, 6, 7, 8, 9,\
+                                               10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCSIZE                512
+#define CONFIG_SYS_NAND_ECCBYTES       3
+#define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS    0x80000
+#endif
+
 #endif /* __IGEP00X0_H */