/*
* High Level Configuration Options
*/
-#define CONFIG_BOOT_RETRY_TIME 900
-#define CONFIG_BOOT_RETRY_MIN 30
-#define CONFIG_RESET_TO_RETRY
#define CONFIG_SYS_SICRH 0x00000000
#define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D)
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
- - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
* Internal Definitions
* Manually set up DDR parameters,
* as this board has not the SPD connected to I2C.
*/
-#define CONFIG_SYS_DDR_SIZE 256 /* MB */
+#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */
#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\
0x00010000 |\
CSCONFIG_ROW_BIT_13 |\
/*
* NOR FLASH setup
*/
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
#define CONFIG_FLASH_SHOW_PROGRESS 50
#define CONFIG_SYS_FLASH_BASE 0xFF800000
#define CONFIG_SYS_FLASH_SIZE 8
-
-#define CONFIG_SYS_MAX_FLASH_SECT 128
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500
-
/*
* NAND FLASH setup
*/
#define CONFIG_SYS_MRAM_BASE 0xE2000000
#define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */
-#define CONFIG_SYS_OR_TIMING_MRAM
-
-
/*
* CPLD setup
*/
#define CONFIG_SYS_CPLD_BASE 0xE3000000
-#define CONFIG_SYS_CPLD_SIZE 0x8000
-
-#define CONFIG_SYS_OR_TIMING_MRAM
-
/*
* HW-Watchdog
* Ethernet setup
*/
#ifdef CONFIG_TSEC1
-#define CONFIG_HAS_ETH0
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define TSEC1_PHY_ADDR 0x1
#endif
#ifdef CONFIG_TSEC2
-#define CONFIG_HAS_ETH1
#define CONFIG_TSEC2_NAME "TSEC1"
-#define CONFIG_SYS_TSEC2_OFFSET 0x25000
#define TSEC2_PHY_ADDR 0x3
#define TSEC2_FLAGS TSEC_GIGABIT
#define TSEC2_PHYIDX 0
#endif
-#define CONFIG_ETHPRIME "TSEC1"
/*
* Serial Port
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
-#define CONFIG_HAS_FSL_DR_USB
#define CONFIG_SYS_SCCR_USBDRCM 3
/*
/*
* The reserved memory
*/
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
/*
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_LOADS_ECHO
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
"${netmask}:${hostname}:${netdev}:off " \
"console=${console},${baudrate} ${othbootargs}\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
- "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
"\0"
/* UBI Support */