#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_HYMOD 1 /* ...on a Hymod board */
+#define CONFIG_CPM2 1 /* Has a CPM2 */
+
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
+#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
#define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
#undef CONFIG_ETHER_NONE /* define if ether on something else */
#define CONFIG_ETHER_INDEX 1 /* which channel for ether */
+#define CONFIG_ETHER_LOOPBACK_TEST /* add ether external loopback test */
+
+#ifdef CONFIG_ETHER_ON_FCC
#if (CONFIG_ETHER_INDEX == 1)
* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
* - Enable Full Duplex in FSMR
*/
-# define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
-# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11)
-# define CFG_CPMFCR_RAMTYPE 0
-# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
+# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11)
+# define CONFIG_SYS_CPMFCR_RAMTYPE 0
+# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+# define MDIO_PORT 0 /* Port A */
+# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
+ (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+# define MDC_DECLARE MDIO_DECLARE
+
+# define MDIO_DATA_PINMASK 0x00040000 /* Pin 13 */
+# define MDIO_CLCK_PINMASK 0x00080000 /* Pin 12 */
#elif (CONFIG_ETHER_INDEX == 2)
* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
* - Enable Full Duplex in FSMR
*/
-# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CFG_CPMFCR_RAMTYPE 0
-# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
+# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CPMFCR_RAMTYPE 0
+# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+# define MDIO_PORT 0 /* Port A */
+# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
+ (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+# define MDC_DECLARE MDIO_DECLARE
+
+# define MDIO_DATA_PINMASK 0x00000040 /* Pin 25 */
+# define MDIO_CLCK_PINMASK 0x00000080 /* Pin 24 */
#elif (CONFIG_ETHER_INDEX == 3)
* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
* - Enable Full Duplex in FSMR
*/
-# define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
-# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
-# define CFG_CPMFCR_RAMTYPE 0
-# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
+# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
+# define CONFIG_SYS_CPMFCR_RAMTYPE 0
+# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+# define MDIO_PORT 0 /* Port A */
+# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
+ (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+# define MDC_DECLARE MDIO_DECLARE
+
+# define MDIO_DATA_PINMASK 0x00000100 /* Pin 23 */
+# define MDIO_CLCK_PINMASK 0x00000200 /* Pin 22 */
#endif /* CONFIG_ETHER_INDEX */
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
+
+#define MDIO_ACTIVE (iop->pdir |= MDIO_DATA_PINMASK)
+#define MDIO_TRISTATE (iop->pdir &= ~MDIO_DATA_PINMASK)
+#define MDIO_READ ((iop->pdat & MDIO_DATA_PINMASK) != 0)
+
+#define MDIO(bit) if(bit) iop->pdat |= MDIO_DATA_PINMASK; \
+ else iop->pdat &= ~MDIO_DATA_PINMASK
+
+#define MDC(bit) if(bit) iop->pdat |= MDIO_CLCK_PINMASK; \
+ else iop->pdat &= ~MDIO_CLCK_PINMASK
+
+#define MIIDELAY udelay(1)
+
+#endif /* CONFIG_ETHER_ON_FCC */
+
/* other options */
#define CONFIG_HARD_I2C 1 /* To enable I2C hardware support */
+#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
#ifdef DEBUG
#if defined(CONFIG_CONS_USE_EXTC)
#define CONFIG_BAUDRATE 115200
#else
-#define CONFIG_BAUDRATE 38400
+#define CONFIG_BAUDRATE 9600
#endif
/* default ip addresses - these will be overridden */
#define CONFIG_IPADDR 192.168.1.1 /* hymod "boot" address */
#define CONFIG_SERVERIP 192.168.1.254 /* hymod "server" address */
-#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
- CFG_CMD_BEDBUG | \
- CFG_CMD_DOC | \
- CFG_CMD_ELF | \
- CFG_CMD_FDC | \
- CFG_CMD_HWFLOW | \
- CFG_CMD_IDE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_MII | \
- CFG_CMD_PCMCIA | \
- CFG_CMD_PCI | \
- CFG_CMD_USB | \
- CFG_CMD_SCSI | \
- CFG_CMD_SPI | \
- CFG_CMD_VFD | \
- CFG_CMD_DTT ) )
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CONFIG_LAST_STAGE_INIT
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_KGDB
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_XIMG
#ifdef DEBUG
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#define CONFIG_BOOT_RETRY_TIME 30 /* retry autoboot after 30 secs */
+#define CONFIG_BOOT_RETRY_MIN 1 /* can go down to 1 second timeout */
+/* Be selective on what keys can delay or stop the autoboot process
+ * To stop use: " "
+ */
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \
+ "press <SPACE> to stop\n", bootdelay
+#define CONFIG_AUTOBOOT_STOP_STR " "
+#undef CONFIG_AUTOBOOT_DELAY_STR
+#define DEBUG_BOOTKEYS 0
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
# if defined(CONFIG_KGDB_USE_EXTC)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
# else
-#define CONFIG_KGDB_BAUDRATE 38400 /* speed to run kgdb serial port at */
+#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */
# endif
#endif
/*
* Hymod specific configurable options
*/
-#undef CFG_HYMOD_DBLEDS /* walk mezz board LEDs */
+#undef CONFIG_SYS_HYMOD_DBLEDS /* walk mezz board LEDs */
/*
* Miscellaneous configurable options
*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x03c00000 /* 4 ... 60 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x03c00000 /* 4 ... 60 MB in DRAM */
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-#define CFG_I2C_SPEED 50000
-#define CFG_I2C_SLAVE 0x7e
+#define CONFIG_SYS_I2C_SPEED 50000
+#define CONFIG_SYS_I2C_SLAVE 0x7e
/* these are for the ST M24C02 2kbit serial i2c eeprom */
-#define CFG_I2C_EEPROM_ADDR 0x50 /* base address */
-#define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
-#define CFG_I2C_RTC_ADDR 0x51 /* philips PCF8563 RTC address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
+/* mask of address bits that overflow into the "EEPROM chip address" */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
+
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16 byte write page size */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+
+#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* hymod has two eeproms */
+
+#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* philips PCF8563 RTC address */
+
+/*
+ * standard dtt sensor configuration - bottom bit will determine local or
+ * remote sensor of the ADM1021, the rest determines index into
+ * CONFIG_SYS_DTT_ADM1021 array below.
+ *
+ * On HYMOD board, the remote sensor should be connected to the MPC8260
+ * temperature diode thingy, but an errata said this didn't work and
+ * should be disabled - so it isn't connected.
+ */
+#if 0
+#define CONFIG_DTT_SENSORS { 0, 1 }
+#else
+#define CONFIG_DTT_SENSORS { 0 }
+#endif
+
+/*
+ * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
+ * there will be one entry in this array for each two (dummy) sensors in
+ * CONFIG_DTT_SENSORS.
+ *
+ * For HYMOD board:
+ * - only one ADM1021
+ * - i2c addr 0x2a (both ADD0 and ADD1 are N/C)
+ * - conversion rate 0x02 = 0.25 conversions/second
+ * - ALERT ouput disabled
+ * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
+ * - remote temp sensor disabled (see comment for CONFIG_DTT_SENSORS above)
+ */
+#define CONFIG_SYS_DTT_ADM1021 { { 0x2a, 0x02, 0, 1, 0, 85, 0, } }
/*
* Low Level Configuration Settings
/*-----------------------------------------------------------------------
* Hard Reset Configuration Words
*
- * if you change bits in the HRCW, you must also change the CFG_*
+ * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
* defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
*/
#ifdef DEBUG
-#define CFG_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
+#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
HRCW_MODCK_H0010)
#else
-#define CFG_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
+#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
HRCW_MODCK_H0101)
#endif
/* no slaves so just duplicate the master hrcw */
-#define CFG_HRCW_SLAVE1 CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE2 CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE3 CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE4 CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE5 CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE6 CFG_HRCW_MASTER
-#define CFG_HRCW_SLAVE7 CFG_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE1 CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE2 CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE3 CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE4 CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE5 CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE6 CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE7 CONFIG_SYS_HRCW_MASTER
/*-----------------------------------------------------------------------
* Internal Memory Mapped Register
*/
-#define CFG_IMMR 0xF0000000
+#define CONFIG_SYS_IMMR 0xF0000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CFG_INIT_RAM_ADDR CFG_IMMR
-#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
-#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CFG_SDRAM_BASE 0x00000000
-#define CFG_FLASH_BASE TEXT_BASE
-#define CFG_MONITOR_BASE TEXT_BASE
-#define CFG_FPGA_BASE 0x80000000
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_FPGA_BASE 0x80000000
/*
- * unfortunately, CFG_MONITOR_LEN must include the
+ * unfortunately, CONFIG_SYS_MONITOR_LEN must include the
* (very large i.e. 256kB) environment flash sector
*/
-#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor*/
-#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
+#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor*/
+#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
/*-----------------------------------------------------------------------
* FLASH organization
*/
-#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
-#define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */
-
-#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */
-#define CFG_FLASH_TYPE FLASH_28F640J3A
-#define CFG_FLASH_ID (INTEL_ID_28F640J3A & 0xff)
-#define CFG_FLASH_NBLOCKS 64
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
-#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */
-#define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE)
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
+#define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
+#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
#endif
/*-----------------------------------------------------------------------
*
* HID1 has only read-only information - nothing to set.
*/
-#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
HID0_IFEM|HID0_ABE)
#ifdef DEBUG
-#define CFG_HID0_FINAL 0
+#define CONFIG_SYS_HID0_FINAL 0
#else
-#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
#endif
-#define CFG_HID2 0
+#define CONFIG_SYS_HID2 0
/*-----------------------------------------------------------------------
* RMR - Reset Mode Register 5-5
* turn on Checkstop Reset Enable
*/
#ifdef DEBUG
-#define CFG_RMR 0
+#define CONFIG_SYS_RMR 0
#else
-#define CFG_RMR RMR_CSRE
+#define CONFIG_SYS_RMR RMR_CSRE
#endif
/*-----------------------------------------------------------------------
* BCR - Bus Configuration 4-25
*-----------------------------------------------------------------------
*/
-#define CFG_BCR (BCR_ETM)
+#define CONFIG_SYS_BCR (BCR_ETM)
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration 4-31
*-----------------------------------------------------------------------
*/
-#define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_L2CPC01|\
+#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_L2CPC01|\
SIUMCR_APPC10|SIUMCR_MMR11)
/*-----------------------------------------------------------------------
* Watchdog & Bus Monitor Timer max, 60x & Local Bus Monitor enable
*/
#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
#else
-#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
SYPCR_SWRI|SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
* and enable Time Counter
*/
-#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 4-42
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
* Periodic timer
*/
-#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
/*-----------------------------------------------------------------------
* SCCR - System Clock Control 9-8
*-----------------------------------------------------------------------
* Ensure DFBRG is Divide by 16
*/
-#define CFG_SCCR (SCCR_DFBRG01)
+#define CONFIG_SYS_SCCR (SCCR_DFBRG01)
/*-----------------------------------------------------------------------
* RCCR - RISC Controller Configuration 13-7
*-----------------------------------------------------------------------
*/
-#define CFG_RCCR 0
+#define CONFIG_SYS_RCCR 0
/*
* Init Memory Controller:
*/
/* 32 bit, read-write, GPCM on 60x bus */
-#define CFG_BR0_PRELIM ((CFG_FLASH_BASE&BRx_BA_MSK)|\
+#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE&BRx_BA_MSK)|\
BRx_PS_32|BRx_MS_GPCM_P|BRx_V)
/* up to 32 Mb */
-#define CFG_OR0_PRELIM (MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
+#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
/*
* Bank 2 - SDRAM
* address lines to be configured to the required multiplexing scheme."
*/
-#define CFG_SDRAM_SIZE 64
+#define CONFIG_SYS_SDRAM_SIZE 64
/* 64 bit, read-write, SDRAM on 60x bus */
-#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE&BRx_BA_MSK)|\
+#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE&BRx_BA_MSK)|\
BRx_PS_64|BRx_MS_SDRAM_P|BRx_V)
/* 64 Mb, 4 int banks per dev, row start addr bit = A6, 12 row addr lines */
-#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM_SIZE)|\
+#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM_SIZE)|\
ORxS_BPD_4|ORxS_ROWST_PBI1_A6|ORxS_NUMR_12)
/*
* was written is 1 clock, CAS Latency is 2.
*/
-#define CFG_PSDMR (PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\
+#define CONFIG_SYS_PSDMR (PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\
PSDMR_BSMA_A14_A16|PSDMR_SDA10_PBI1_A7|\
PSDMR_RFRC_6_CLK|PSDMR_PRETOACT_2W|\
PSDMR_ACTTORW_2W|PSDMR_LDOTOPRE_1C|\
*/
#ifdef DEBUG
-#define CFG_PSRT 39
-#define CFG_MPTPR MPTPR_PTP_DIV8
+#define CONFIG_SYS_PSRT 39
+#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV8
#else
-#define CFG_PSRT 31
-#define CFG_MPTPR MPTPR_PTP_DIV32
+#define CONFIG_SYS_PSRT 31
+#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
#endif
/*
*/
/* all the bank sizes must be a power of two, greater or equal to 32768 */
-#define FPGA_MAIN_CFG_BASE (CFG_FPGA_BASE)
+#define FPGA_MAIN_CFG_BASE (CONFIG_SYS_FPGA_BASE)
#define FPGA_MAIN_CFG_SIZE 32768
#define FPGA_MAIN_REG_BASE (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE)
#define FPGA_MAIN_REG_SIZE 32768
#define FPGA_MEZZ_CFG_SIZE 32768
/* 8 bit, read-write, UPMC */
-#define CFG_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
+#define CONFIG_SYS_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
/* up to 32Kbyte, burst inhibit */
-#define CFG_OR3_PRELIM (P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI)
+#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI)
/* 32 bit, read-write, GPCM */
-#define CFG_BR4_PRELIM (FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V)
+#define CONFIG_SYS_BR4_PRELIM (FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V)
/* up to 32Kbyte */
-#define CFG_OR4_PRELIM (P2SZ_TO_AM(FPGA_MAIN_REG_SIZE))
+#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(FPGA_MAIN_REG_SIZE))
/* 32 bit, read-write, UPMB */
-#define CFG_BR5_PRELIM (FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V)
+#define CONFIG_SYS_BR5_PRELIM (FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V)
/* up to 32Kbyte */
-#define CFG_OR5_PRELIM (P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI)
+#define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI)
/* 8 bit, write-only, UPMC */
-#define CFG_BR6_PRELIM (FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
+#define CONFIG_SYS_BR6_PRELIM (FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
/* up to 32Kbyte, burst inhibit */
-#define CFG_OR6_PRELIM (P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI)
+#define CONFIG_SYS_OR6_PRELIM (P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI)
/*-----------------------------------------------------------------------
* MBMR - Machine B Mode 10-27
*-----------------------------------------------------------------------
*/
-#define CFG_MBMR (MxMR_BSEL|MxMR_OP_NORM) /* XXX - needs more */
+#define CONFIG_SYS_MBMR (MxMR_BSEL|MxMR_OP_NORM) /* XXX - needs more */
/*-----------------------------------------------------------------------
* MCMR - Machine C Mode 10-27
*-----------------------------------------------------------------------
*/
-#define CFG_MCMR (MxMR_BSEL|MxMR_DSx_2_CYCL) /* XXX - needs more */
+#define CONFIG_SYS_MCMR (MxMR_BSEL|MxMR_DSx_2_CYCL) /* XXX - needs more */
/*
* FPGA I/O Port/Bit information
#define FPGA_MEZZ_ENABLE_PIN 3 /* PA3 */
/*
- * Internal Definitions
+ * FPGA Interrupt configuration
+ */
+#define FPGA_MAIN_IRQ SIU_INT_IRQ2
+
+/*
+ * JFFS2 partitions
*
- * Boot Flags
*/
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+/* No command line, one static partition, whole device */
+#undef CONFIG_CMD_MTDPARTS
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT ""
+#define MTDPARTS_DEFAULT ""
+*/
#endif /* __CONFIG_H */
projects / platform / kernel / u-boot.git / blobdiff