#define CONFIG_PORT_ADDR 0xF0000500
-/*-----------------------------------------------------------------------
- * Cache Configuration
- *----------------------------------------------------------------------*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405GPr CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-
/*
* Internal Definitions
*