global: Migrate CONFIG_STACKBASE to CFG

[platform/kernel/u-boot.git] / include / configs / grpeach.h

diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h
index 347845f..8de4a36 100644 (file)
--- a/include/configs/grpeach.h
+++ b/include/configs/grpeach.h
@@ -11,22 +11,17 @@
 /* Board Clock , P1 clock frequency (XTAL=13.33MHz) */
 
 /* Miscellaneous */
-#define CONFIG_SYS_PBSIZE      256
 
 /* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
-#define CONFIG_SYS_SDRAM_BASE          0x20000000
-#define CONFIG_SYS_SDRAM_SIZE          (10 * 1024 * 1024)
-#define CONFIG_SYS_INIT_SP_ADDR                \
-       (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 1024 * 1024)
-
-#define CONFIG_SYS_MONITOR_LEN         (512 * 1024)
+#define CFG_SYS_SDRAM_BASE             0x20000000
+#define CFG_SYS_SDRAM_SIZE             (10 * 1024 * 1024)
 
 /* Network interface */
-#define CONFIG_SH_ETHER_USE_PORT       0
-#define CONFIG_SH_ETHER_PHY_ADDR       0
-#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
-#define CONFIG_SH_ETHER_CACHE_WRITEBACK
-#define CONFIG_SH_ETHER_CACHE_INVALIDATE
-#define CONFIG_SH_ETHER_ALIGNE_SIZE    64
+#define CFG_SH_ETHER_USE_PORT  0
+#define CFG_SH_ETHER_PHY_ADDR  0
+#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
+#define CFG_SH_ETHER_CACHE_WRITEBACK
+#define CFG_SH_ETHER_CACHE_INVALIDATE
+#define CFG_SH_ETHER_ALIGNE_SIZE       64
 
 #endif /* __GRPEACH_H */