fsl_esdhc: Add the workaround for erratum ESDHC111 (enable on P4080)

[platform/kernel/u-boot.git] / include / configs / favr-32-ezkit.h

diff --git a/include/configs/favr-32-ezkit.h b/include/configs/favr-32-ezkit.h
index 3cef419..1c381c7 100644 (file)
--- a/include/configs/favr-32-ezkit.h
+++ b/include/configs/favr-32-ezkit.h
@@ -70,6 +70,9 @@
  */
 #define CONFIG_SYS_CLKDIV_PBB                  1
 
+/* Reserve VM regions for SDRAM and NOR flash */
+#define CONFIG_SYS_NR_VM_REGIONS               2
+
 /*
  * The PLLOPT register controls the PLL like this:
  *   icp = PLLOPT<2>
@@ -139,14 +142,14 @@
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MMC
 
-#undef CONFIG_CMD_AUTOSCRIPT
 #undef CONFIG_CMD_FPGA
 #undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_SOURCE
 #undef CONFIG_CMD_XIMG
 
 #define CONFIG_ATMEL_USART             1
 #define CONFIG_MACB                    1
-#define CONFIG_PIO2                    1
+#define CONFIG_PORTMUX_PIO             1
 #define CONFIG_SYS_NR_PIOS                     5
 #define CONFIG_SYS_HSDRAMC                     1
 #define CONFIG_MMC                     1