#ifndef __CONFIG_EXYNOS78x0_COMMON_H
#define __CONFIG_EXYNOS78x0_COMMON_H
-/* High Level Configuration Options */
-#define CONFIG_SAMSUNG /* in a SAMSUNG core */
-#define CONFIG_S5P
-
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <linux/sizes.h>
/* Miscellaneous configurable options */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */
-
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/* Timer input clock frequency */
-#define COUNTER_FREQUENCY 26000000
-
-/* Device Tree */
-#define CONFIG_DEVICE_TREE_LIST "EXYNOS78x0-a5y17lte"
#define CPU_RELEASE_ADDR secondary_boot_addr
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
{9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600}
-#define CONFIG_BOARD_COMMON
-
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_SDRAM_BASE 0x40000000
/* DRAM Memory Banks */
#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_9 (CONFIG_SYS_SDRAM_BASE + (8 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_9 (CFG_SYS_SDRAM_BASE + (8 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_9_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_10 (CONFIG_SYS_SDRAM_BASE + (9 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_10 (CFG_SYS_SDRAM_BASE + (9 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_10_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_11 (CONFIG_SYS_SDRAM_BASE + (10 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_11 (CFG_SYS_SDRAM_BASE + (10 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_11_SIZE SDRAM_BANK_SIZE
-#define PHYS_SDRAM_12 (CONFIG_SYS_SDRAM_BASE + (11 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_12 (CFG_SYS_SDRAM_BASE + (11 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_12_SIZE SDRAM_BANK_SIZE
#ifndef MEM_LAYOUT_ENV_SETTINGS
#define EXYNOS_FDTFILE_SETTING
#endif
+/* Cannot use bootdelay > 0, because timer is not working */
#define EXTRA_ENV_SETTINGS \
+ "bootdelay=0\0" \
+ "bootcmd=source $prevbl_initrd_start_addr:bootscript\0" \
EXYNOS_DEVICE_SETTINGS \
EXYNOS_FDTFILE_SETTING \
MEM_LAYOUT_ENV_SETTINGS
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
EXTRA_ENV_SETTINGS
#endif /* __CONFIG_EXYNOS78x0_COMMON_H */