/* MMC SPL */
#define COPY_BL2_FNPTR_ADDR 0x02020030
-#define CONFIG_RD_LVL
-
#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
/* Ethernet Controllor Driver */
#ifdef CONFIG_CMD_NET
-#define CONFIG_ENV_SROM_BANK 1
+#define CFG_ENV_SROM_BANK 1
#endif /*CONFIG_CMD_NET*/
/* Enable Time Command */
#define EXYNOS_FDTFILE_SETTING
#endif
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
EXYNOS_DEVICE_SETTINGS \
EXYNOS_FDTFILE_SETTING \
MEM_LAYOUT_ENV_SETTINGS \