global: Migrate CONFIG_MXC_UART_BASE to CFG

[platform/kernel/u-boot.git] / include / configs / exynos5-common.h

diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h
index 7ab821d..ec09f6c 100644 (file)
--- a/include/configs/exynos5-common.h
+++ b/include/configs/exynos5-common.h
@@ -8,15 +8,8 @@
 #ifndef __CONFIG_EXYNOS5_COMMON_H
 #define __CONFIG_EXYNOS5_COMMON_H
 
-#define CONFIG_EXYNOS5                 /* Exynos5 Family */
-
 #include "exynos-common.h"
 
-#define CONFIG_EXYNOS_SPL
-
-/* Enable ACE acceleration for SHA1 and SHA256 */
-#define CONFIG_EXYNOS_ACE_SHA
-
 /* Power Down Modes */
 #define S5P_CHECK_SLEEP                        0x00000BAD
 #define S5P_CHECK_DIDLE                        0xBAD00000
@@ -31,36 +24,31 @@
 /* select serial console configuration */
 #define EXYNOS5_DEFAULT_UART_OFFSET    0x010000
 
-/* Thermal Management Unit */
-#define CONFIG_EXYNOS_TMU
-
 /* MMC SPL */
 #define COPY_BL2_FNPTR_ADDR    0x02020030
 
-#define CONFIG_RD_LVL
-
-#define PHYS_SDRAM_1           CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1           CFG_SYS_SDRAM_BASE
 #define PHYS_SDRAM_1_SIZE      SDRAM_BANK_SIZE
-#define PHYS_SDRAM_2           (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2           (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
 #define PHYS_SDRAM_2_SIZE      SDRAM_BANK_SIZE
-#define PHYS_SDRAM_3           (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3           (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_3_SIZE      SDRAM_BANK_SIZE
-#define PHYS_SDRAM_4           (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4           (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_4_SIZE      SDRAM_BANK_SIZE
-#define PHYS_SDRAM_5           (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5           (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_5_SIZE      SDRAM_BANK_SIZE
-#define PHYS_SDRAM_6           (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6           (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_6_SIZE      SDRAM_BANK_SIZE
-#define PHYS_SDRAM_7           (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7           (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_7_SIZE      SDRAM_BANK_SIZE
-#define PHYS_SDRAM_8           (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8           (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
 #define PHYS_SDRAM_8_SIZE      SDRAM_BANK_SIZE
 
 /* SPI */
 
 /* Ethernet Controllor Driver */
 #ifdef CONFIG_CMD_NET
-#define CONFIG_ENV_SROM_BANK           1
+#define CFG_ENV_SROM_BANK              1
 #endif /*CONFIG_CMD_NET*/
 
 /* Enable Time Command */
@@ -68,7 +56,6 @@
 /* USB */
 
 /* USB boot mode */
-#define CONFIG_USB_BOOTING
 #define EXYNOS_COPY_USB_FNPTR_ADDR     0x02020070
 #define EXYNOS_USB_SECONDARY_BOOT      0xfeed0002
 #define EXYNOS_IRAM_SECONDARY_BASE     0x02020018
@@ -104,7 +91,7 @@
 #define EXYNOS_FDTFILE_SETTING
 #endif
 
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
        EXYNOS_DEVICE_SETTINGS \
        EXYNOS_FDTFILE_SETTING \
        MEM_LAYOUT_ENV_SETTINGS \