board: freescale: p1_p2_rdb_pc: Define SW macros for lower and upper NOR banks

[platform/kernel/u-boot.git] / include / configs / exynos-common.h

diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h
index 95aaa74..dd1cbd7 100644 (file)
--- a/include/configs/exynos-common.h
+++ b/include/configs/exynos-common.h
@@ -19,8 +19,6 @@
 /* Keep L2 Cache Disabled */
 
 /* input clock of PLL: 24MHz input clock */
-#define CONFIG_SYS_CLK_FREQ            24000000
-#define COUNTER_FREQUENCY              CONFIG_SYS_CLK_FREQ
 
 /* select serial console configuration */