/*
* board/config.h - configuration options, board specific
*
- * Note: my board is a "SBC 8260 H, V.1.1"
- * - 64M 60x Bus SDRAM
- * - 32M Local Bus SDRAM
- * - 16M Flash (4 x AM29DL323DB90WDI)
- * - 128k NVRAM with RTC
+ * "EP8260 H, V.1.1"
+ * - 64M 60x Bus SDRAM
+ * - 32M Local Bus SDRAM
+ * - 16M Flash (4 x AM29DL323DB90WDI)
+ * - 128k NVRAM with RTC
+ *
+ * "EP8260 H2, V.1.3" (CFG_EP8260_H2)
+ * - 300MHz/133MHz/66MHz
+ * - 64M 60x Bus SDRAM
+ * - 32M Local Bus SDRAM
+ * - 32M Flash
+ * - 128k NVRAM with RTC
*/
#ifndef __CONFIG_H
#define __CONFIG_H
+/* Define this to enable support the EP8260 H2 version */
+#define CFG_EP8260_H2 1
+/* #undef CFG_EP8260_H2 */
+
+#define CONFIG_CPM2 1 /* Has a CPM2 */
+
/* What is the oscillator's (UX2) frequency in Hz? */
#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
* 0x6 0x1 66 133 266
* 0x6 0x2 66 133 300
*/
-#define CFG_SBC_MODCK_H 0x05
+#ifdef CFG_EP8260_H2
+#define CFG_SBC_MODCK_H (HRCW_MODCK_H0110)
+#else
+#define CFG_SBC_MODCK_H (HRCW_MODCK_H0110)
+#endif
/* Define this if you want to boot from 0x00000100. If you don't define
* this, you will need to program the bootloader to 0xfff00000, and
* The main FLASH is whichever is connected to *CS0. U-Boot expects
* this to be the SIMM.
*/
+#ifdef CFG_EP8260_H2
+#define CFG_FLASH0_BASE 0xFE000000
+#define CFG_FLASH0_SIZE 32
+#else
#define CFG_FLASH0_BASE 0xFF000000
#define CFG_FLASH0_SIZE 16
+#endif
/* What should the base address of the secondary FLASH be and how big
* is it (in Mbytes)? The secondary FLASH is whichever is connected
/* What should be the base address of NVRAM and how big is
* it (in Bytes)
*/
-#define CFG_NVRAM_BASE_ADDR 0xFa080000
+#define CFG_NVRAM_BASE_ADDR 0xFA080000
#define CFG_NVRAM_SIZE (128*1024)-16
/* The RTC is a Dallas DS1556
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
* put in the same sector as U-Boot, and changing variables
* will erase U-Boot temporarily
*/
-#define CFG_ENV_IN_OWN_SECT
+#define CONFIG_ENV_IN_OWN_SECT
/* Define to allow the user to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
/* What should the console's baud rate be? */
-/* #define CONFIG_BAUDRATE 57600 */
+#ifdef CFG_EP8260_H2
+#define CONFIG_BAUDRATE 9600
+#else
#define CONFIG_BAUDRATE 115200
+#endif
/* Ethernet MAC address */
#define CONFIG_ETHADDR 00:10:EC:00:30:8C
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
-/* What U-Boot subsytems do you want enabled? */
+
/*
-*/
-#define CONFIG_COMMANDS ( CFG_CMD_ALL & \
- ~CFG_CMD_BMP & \
- ~CFG_CMD_BSP & \
- ~CFG_CMD_DCR & \
- ~CFG_CMD_DHCP & \
- ~CFG_CMD_DOC & \
- ~CFG_CMD_EEPROM & \
- ~CFG_CMD_FDC & \
- ~CFG_CMD_FDOS & \
- ~CFG_CMD_HWFLOW & \
- ~CFG_CMD_IDE & \
- ~CFG_CMD_JFFS2 & \
- ~CFG_CMD_KGDB & \
- ~CFG_CMD_MII & \
- ~CFG_CMD_NAND & \
- ~CFG_CMD_PCI & \
- ~CFG_CMD_PCMCIA & \
- ~CFG_CMD_SCSI & \
- ~CFG_CMD_SPI & \
- ~CFG_CMD_USB & \
- ~CFG_CMD_VFD & \
- ~CFG_CMD_DTT )
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
+#undef CONFIG_CMD_DCR
+#undef CONFIG_CMD_XIMG
/* Where do the internal registers live? */
#define CFG_IMMR 0xF0000000
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_EP8260 11 /* on an Embedded Planet EP8260 Board, Rev. 11 */
-#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
/*
* Miscellaneous configurable options
*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
# define CFG_SBC_HRCW_BOOT_FLAGS (0x00000000)
#endif /* defined(CFG_SBC_BOOT_LOW) */
-/* get the HRCW ISB field from CFG_IMMR */
-/*
-#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\
- ((CFG_IMMR & 0x01000000) >> 7) |\
- ((CFG_IMMR & 0x00100000) >> 4) )
+#ifdef CFG_EP8260_H2
+/* get the HRCW ISB field from CFG_DEFAULT_IMMR */
+#define CFG_SBC_HRCW_IMMR ( ((CFG_DEFAULT_IMMR & 0x10000000) >> 10) |\
+ ((CFG_DEFAULT_IMMR & 0x01000000) >> 7) |\
+ ((CFG_DEFAULT_IMMR & 0x00100000) >> 4) )
#define CFG_HRCW_MASTER (HRCW_EBM |\
- HRCW_L2CPC01 |\
+ HRCW_L2CPC01 |\
CFG_SBC_HRCW_IMMR |\
HRCW_APPC10 |\
HRCW_CS10PC01 |\
- HRCW_MODCK_H0101 |\
+ CFG_SBC_MODCK_H |\
CFG_SBC_HRCW_BOOT_FLAGS)
-*/
+#else
#define CFG_HRCW_MASTER 0x10400245
+#endif
/* no slaves */
#define CFG_HRCW_SLAVE1 0
* FLASH and environment organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#ifdef CFG_EP8260_H2
+#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
+#else
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
+#endif
+#ifdef CFG_EP8260_H2
+#define CFG_FLASH_ERASE_TOUT 240000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+#else
#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
+#endif
#ifndef CFG_RAMBOOT
-# define CFG_ENV_IS_IN_FLASH 1
+# define CONFIG_ENV_IS_IN_FLASH 1
-# ifdef CFG_ENV_IN_OWN_SECT
-# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
-# define CFG_ENV_SECT_SIZE 0x40000
+# ifdef CONFIG_ENV_IN_OWN_SECT
+# define CONFIG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+# define CONFIG_ENV_SECT_SIZE 0x40000
# else
-# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
-# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
-# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
-# endif /* CFG_ENV_IN_OWN_SECT */
+# define CONFIG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
+# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
+# define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
+# endif /* CONFIG_ENV_IN_OWN_SECT */
#else
-# define CFG_ENV_IS_IN_NVRAM 1
-# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
-# define CFG_ENV_SIZE 0x200
+# define CONFIG_ENV_IS_IN_NVRAM 1
+# define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
+# define CONFIG_ENV_SIZE 0x200
#endif /* CFG_RAMBOOT */
/*-----------------------------------------------------------------------
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
* BCR - Bus Configuration 4-25
*-----------------------------------------------------------------------
*/
-/*#define CFG_BCR (BCR_EBM |\
+#define CFG_BCR (BCR_EBM |\
BCR_PLDP |\
BCR_EAV |\
- BCR_NPQM1)
-*/
-#define CFG_BCR 0x80C08000
+ BCR_NPQM0)
+
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration 4-31
*-----------------------------------------------------------------------
*/
-
#define CFG_SIUMCR (SIUMCR_L2CPC01 |\
- SIUMCR_APPC10 |\
- SIUMCR_CS10PC01)
-
+ SIUMCR_APPC10 |\
+ SIUMCR_CS10PC01)
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9
*-----------------------------------------------------------------------
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
*/
+#ifdef CFG_EP8260_H2
+/* TBD: Find out why setting the BMT to 0xff causes the FCC to
+ * generate TX buffer underrun errors for large packets under
+ * Linux
+ */
+#define CFG_SYPCR_BMT 0x00000600
+#else
+#define CFG_SYPCR_BMT SYPCR_BMT
+#endif
+
#ifdef CFG_LSDRAM
#define CFG_SYPCR (SYPCR_SWTC |\
- SYPCR_BMT |\
- SYPCR_PBME |\
- SYPCR_LBME |\
- SYPCR_SWP)
+ CFG_SYPCR_BMT |\
+ SYPCR_PBME |\
+ SYPCR_LBME |\
+ SYPCR_SWP)
#else
#define CFG_SYPCR (SYPCR_SWTC |\
- SYPCR_BMT |\
- SYPCR_PBME |\
- SYPCR_SWP)
+ CFG_SYPCR_BMT |\
+ SYPCR_PBME |\
+ SYPCR_SWP)
#endif
+
/*-----------------------------------------------------------------------
* TMCNTSC - Time Counter Status and Control 4-40
*-----------------------------------------------------------------------
* and enable Time Counter
*/
#define CFG_TMCNTSC (TMCNTSC_SEC |\
- TMCNTSC_ALR |\
- TMCNTSC_TCF |\
- TMCNTSC_TCE)
+ TMCNTSC_ALR |\
+ TMCNTSC_TCF |\
+ TMCNTSC_TCE)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 4-42
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
* Periodic timer
*/
-/*#define CFG_PISCR (PISCR_PS |\
- PISCR_PTF |\
- PISCR_PTE)*/
+#ifdef CFG_EP8260_H2
+#define CFG_PISCR (PISCR_PS |\
+ PISCR_PTF |\
+ PISCR_PTE)
+#else
#define CFG_PISCR 0
+#endif
+
/*-----------------------------------------------------------------------
* SCCR - System Clock Control 9-8
*-----------------------------------------------------------------------
*/
+#ifdef CFG_EP8260_H2
+#define CFG_SCCR (SCCR_DFBRG00)
+#else
#define CFG_SCCR (SCCR_DFBRG01)
+#endif
/*-----------------------------------------------------------------------
* RCCR - RISC Controller Configuration 13-7
*
*/
#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
+ BRx_PS_64 |\
BRx_DECC_NONE |\
- BRx_MS_GPCM_P |\
- BRx_V)
+ BRx_MS_GPCM_P |\
+ BRx_V)
#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_6_CLK |\
- ORxG_EHTR)
+ ORxG_CSNT |\
+ ORxG_ACS_DIV1 |\
+ ORxG_SCY_8_CLK |\
+ ORxG_EHTR)
/* Bank 1 - SDRAM
* PSDRAM
*/
#define CFG_BR1_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_SDRAM_P |\
- BRx_V)
+ BRx_PS_64 |\
+ BRx_MS_SDRAM_P |\
+ BRx_V)
#define CFG_OR1_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI1_A6 |\
- ORxS_NUMR_12)
+ ORxS_BPD_4 |\
+ ORxS_ROWST_PBI1_A6 |\
+ ORxS_NUMR_12)
+#ifdef CFG_EP8260_H2
+#define CFG_PSDMR 0xC34E246E
+#else
#define CFG_PSDMR 0xC34E2462
-#define CFG_PSRT 0x64
+#endif
+#define CFG_PSRT 0x64
#ifdef CFG_LSDRAM
/* Bank 2 - SDRAM
*/
#define CFG_BR2_PRELIM ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
- BRx_PS_32 |\
- BRx_MS_SDRAM_L |\
- BRx_V)
+ BRx_PS_32 |\
+ BRx_MS_SDRAM_L |\
+ BRx_V)
#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM1_SIZE) |\
- ORxS_BPD_4 |\
- ORxS_ROWST_PBI0_A9 |\
- ORxS_NUMR_12)
+ ORxS_BPD_4 |\
+ ORxS_ROWST_PBI0_A9 |\
+ ORxS_NUMR_12)
- #define CFG_LSDMR 0x416A2562
+ #define CFG_LSDMR 0x416A2562
#define CFG_LSRT 0x64
#else
#define CFG_LSRT 0x0
* NVRTC and BCSR
*/
#define CFG_BR4_PRELIM ((CFG_REGS_BASE & BRx_BA_MSK) |\
- BRx_PS_8 |\
- BRx_MS_GPCM_P |\
- BRx_V)
+ BRx_PS_8 |\
+ BRx_MS_GPCM_P |\
+ BRx_V)
/*
#define CFG_OR4_PRELIM (ORxG_AM_MSK |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_10_CLK |\
- ORxG_TRLX)
+ ORxG_CSNT |\
+ ORxG_ACS_DIV1 |\
+ ORxG_SCY_10_CLK |\
+ ORxG_TRLX)
*/
#define CFG_OR4_PRELIM 0xfff00854
+#ifdef _NOT_USED_SINCE_NOT_WORKING_
/* Bank 8 - On board registers
* PCMCIA (currently not working!)
*/
#define CFG_BR8_PRELIM ((CFG_REGS_BASE & BRx_BA_MSK) |\
- BRx_PS_16 |\
- BRx_MS_GPCM_P |\
- BRx_V)
+ BRx_PS_16 |\
+ BRx_MS_GPCM_P |\
+ BRx_V)
#define CFG_OR8_PRELIM (ORxG_AM_MSK |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
+ ORxG_CSNT |\
+ ORxG_ACS_DIV1 |\
ORxG_SETA |\
- ORxG_SCY_10_CLK)
+ ORxG_SCY_10_CLK)
+#endif
/*
* Internal Definitions
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT ""
+#define MTDPARTS_DEFAULT ""
+*/
+
#endif /* __CONFIG_H */
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