* High Level Configuration Options (easy to change)
*/
-#define CONFIG_FEROCEON 1 /* CPU Core subversion */
-#define CONFIG_88F5182 1 /* SOC Name */
-
#include <asm/arch/orion5x.h>
/*
* CLKs configurations
* FLASH configuration
*/
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */
#define CONFIG_SYS_FLASH_BASE 0xfff80000
#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */
#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */
#define CONFIG_PHY_BASE_ADR 0x8
-#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
-#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
#endif
/*
*/
#ifdef CONFIG_IDE
#define __io
-/* Needs byte-swapping for ATA data register */
-#define CONFIG_IDE_SWAP_IO
/* Data, registers and alternate blocks are at the same offset */
-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
-#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
-#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
/* Each 8-bit ATA register is aligned to a 4-bytes address */
-#define CONFIG_SYS_ATA_STRIDE 4
/* Controller supports 48-bits LBA addressing */
#define CONFIG_LBA48
/* A single bus, a single device */
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_IDE_MAXDEVICE 1
/* ATA registers base is at SATA controller base */
-#define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE
/* ATA bus 0 is orion5x port 1 on ED Mini V2 */
-#define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET
/* end of IDE defines */
#endif /* CMD_IDE */
* Environment variables configurations
*/
-/*
- * Other required minimal configurations
- */
-
-#define CONFIG_SYS_RESET_ADDRESS 0xffff0000
-
/* Enable command line editing */
/* provide extensive help */