/*--------------------------------------------------------------------------*/
-#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
-#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
-#define CONFIG_EB_CPUX9K2 1 /* on an EP+CPUX9K2 Board */
-#define USE_920T_MMU 1
+#define CONFIG_AT91RM9200 /* It's an Atmel AT91RM9200 SoC */
+#define CONFIG_EB_CPUX9K2 /* on an EP+CPUX9K2 Board */
+#define USE_920T_MMU
-#define CONFIG_VERSION_VARIABLE 1
+#define CONFIG_VERSION_VARIABLE
#define CONFIG_IDENT_STRING " on EB+CPUx9K2"
-#include <asm/arch/hardware.h> /* needed for port definitions */
+#include <asm/hardware.h> /* needed for port definitions */
#define CONFIG_MISC_INIT_R
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define MACH_TYPE_EB_CPUX9K2 1977
+#define CONFIG_MACH_TYPE MACH_TYPE_EB_CPUX9K2
+
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#define CONFIG_SYS_DCACHE_OFF
/*--------------------------------------------------------------------------*/
-#define CONFIG_SYS_TEXT_BASE 0x00000000
+#ifndef CONFIG_RAMBOOT
+#define CONFIG_SYS_TEXT_BASE 0x00000000
+#else
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE 0x21f00000
+#endif
#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
#define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */
#define CONFIG_SYS_U_BOOT_BASE PHYS_FLASH_1
#define CONFIG_SYS_U_BOOT_SIZE 0x60000 /* 384 KBytes */
-
#define CONFIG_BOOT_RETRY_TIME 30
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_STACKSIZE (32*1024) /* regular stack */
-
/*
* ARM asynchronous clock
*/
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
-#define AT91_SLOW_CLOCK 32768 /* slow clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */
#define CONFIG_CMDLINE_TAG 1
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_CMD_PING
#define CONFIG_I2C_CMD_NO_FLAT
#define CONFIG_I2C_CMD_TREE
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
#define CONFIG_SYS_LONGHELP
/*
* Hardware drivers
*/
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_AT91C_PQFP_UHPBUG
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+#define CONFIG_EFI_PARTITION
+
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00300000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
/*
* UART/CONSOLE
*/
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 19200, 38400, 57600, 9600 }
-
#define CONFIG_BAUDRATE 115200
-#define CONFIG_AT91RM9200_USART
-#define CONFIG_DBGU /* define DBGU as console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE ATMEL_BASE_DBGU
+#define CONFIG_USART_ID 0/* ignored in arm */
/*
* network
*/
-#define CONFIG_NET_MULTI 1
#define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_RESET_PHY_R 1
#define CONFIG_SYS_I2C_INIT_BOARD
#define I2C_INIT i2c_init_board();
-#define I2C_ACTIVE writel(AT91_PMX_AA_TWD, &pio->pioa.mddr);
-#define I2C_TRISTATE writel(AT91_PMX_AA_TWD, &pio->pioa.mder);
-#define I2C_READ ((readl(&pio->pioa.pdsr) & AT91_PMX_AA_TWD) != 0)
+#define I2C_ACTIVE writel(ATMEL_PMX_AA_TWD, &pio->pioa.mddr);
+#define I2C_TRISTATE writel(ATMEL_PMX_AA_TWD, &pio->pioa.mder);
+#define I2C_READ ((readl(&pio->pioa.pdsr) & ATMEL_PMX_AA_TWD) != 0)
#define I2C_SDA(bit) \
if (bit) \
- writel(AT91_PMX_AA_TWD, &pio->pioa.sodr); \
+ writel(ATMEL_PMX_AA_TWD, &pio->pioa.sodr); \
else \
- writel(AT91_PMX_AA_TWD, &pio->pioa.codr);
+ writel(ATMEL_PMX_AA_TWD, &pio->pioa.codr);
#define I2C_SCL(bit) \
if (bit) \
- writel(AT91_PMX_AA_TWCK, &pio->pioa.sodr); \
+ writel(ATMEL_PMX_AA_TWCK, &pio->pioa.sodr); \
else \
- writel(AT91_PMX_AA_TWCK, &pio->pioa.codr);
+ writel(ATMEL_PMX_AA_TWCK, &pio->pioa.codr);
#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED)
/* NAND */
-#define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-
/* Status LED's */
#define CONFIG_STATUS_LED 1