* (C) Copyright 2009 Semihalf
* Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software\; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation\; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY\; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program\; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
* High Level Configuration Options
*/
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
+#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFFF00000 boot high (standard configuration)
+ * 0xFE000000 boot low
+ * 0x00100000 boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
+#endif
-#define BOOTFLAG_COLD 0x01
-#define BOOTFLAG_WARM 0x02
+#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
#define CONFIG_SYS_CACHELINE_SIZE 32
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 */
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 9600, 19200, 38400, 57600, 115200, 230400 }
* 0x40000000 - 0x4fffffff - PCI Memory
* 0x50000000 - 0x50ffffff - PCI IO Space
*/
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1
#define CONFIG_PCI_SCAN_SHOW 1
+#define CONFIG_PCI_BOOTDELAY 250
#define CONFIG_PCI_MEM_BUS 0x40000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x01000000
+#define CONFIG_BZIP2
+
/*
- * Partitions
+ * Video
*/
-#define CONFIG_DOS_PARTITION
-#define CONFIG_BZIP2
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_MB862xx
+#define CONFIG_VIDEO_MB862xx_ACCEL
+#define CONFIG_VIDEO_CORALP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
+
+/* Coral-PA clock frequency, geo and other both 133MHz */
+#define CONFIG_SYS_MB862xx_CCF 0x00050000
+/* Video SDRAM parameters */
+#define CONFIG_SYS_MB862xx_MMR 0x11d7fa72
+#endif
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DFL
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_USB
-#if (TEXT_BASE == 0xFF000000)
+#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)
#define CONFIG_SYS_LOWBOOT 1
#endif
/*
* Autobooting
*/
-#define CONFIG_BOOTDELAY 1
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND "run mtcb_start"
/*
- * SPI configuration
- */
-#define CONFIG_HARD_SPI 1
-#define CONFIG_MPC52XX_SPI 1
-
-/*
* I2C configuration
*/
#define CONFIG_HARD_I2C 1
/*
* RTC configuration
*/
+#if defined(CONFIG_DIGSY_REV5)
+#define CONFIG_SYS_I2C_RTC_ADDR 0x56
+#define CONFIG_RTC_RV3029
+/* Enable 5k Ohm trickle charge resistor */
+#define CONFIG_SYS_RV3029_TCR 0x20
+#else
#define CONFIG_RTC_DS1337
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CONFIG_SYS_DS1339_TCR_VAL 0xAB /* diode + 4k resistor */
+#endif
/*
* Flash configuration
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
+#if defined(CONFIG_DIGSY_REV5)
+#define CONFIG_SYS_FLASH_BASE 0xFE000000
+#define CONFIG_SYS_FLASH_BASE_CS1 0xFC000000
+#define CONFIG_SYS_MAX_FLASH_BANKS 2
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
+ CONFIG_SYS_FLASH_BASE_CS1}
+#define CONFIG_SYS_UPDATE_FLASH_SIZE
+#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
+#else
#define CONFIG_SYS_FLASH_BASE 0xFF000000
-#define CONFIG_SYS_FLASH_SIZE 0x01000000
-
#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#endif
+
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_FLASH_16BIT
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_SIZE 0x01000000
#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
#define CONFIG_SYS_FLASH_WRITE_TOUT 500
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
#define OF_CPU "PowerPC,5200@0"
#define OF_SOC "soc5200@f0000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
* Use SRAM until RAM will be available
*/
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_SIZE 4096
#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT 1
#endif
*/
#define CONFIG_MPC5xxx_FEC 1
#define CONFIG_MPC5xxx_FEC_MII100
+#if defined(CONFIG_DIGSY_REV5)
+#define CONFIG_PHY_ADDR 0x01
+#else
#define CONFIG_PHY_ADDR 0x00
+#endif
#define CONFIG_PHY_RESET_DELAY 1000
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_SYS_LONGHELP
#define CONFIG_AUTO_COMPLETE 1
#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_SYS_PROMPT "=> "
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay
-#define CONFIG_AUTOBOOT_DELAY_STR " "
-
-#define CONFIG_LOOPW 1
#define CONFIG_MX_CYCLIC 1
-#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_LOAD_ADDR 0x00100000
-#define CONFIG_SYS_HZ 1000
-
/*
* Various low-level settings
*/
#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_CS0_CFG 0x0002DD00
+#if defined(CONFIG_DIGSY_REV5)
+#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE_CS1
+#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS1_CFG 0x0002DD00
+#endif
+
#define CONFIG_SYS_CS_BURST 0x00000000
#define CONFIG_SYS_CS_DEADCYCLE 0x11111111
*/
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_OHCI_BE_CONTROLLER
-#define CONFIG_USB_STORAGE
#define CONFIG_USB_CLOCK 0x00013333
#define CONFIG_USB_CONFIG 0x00002000
projects / platform / kernel / u-boot.git / blobdiff