+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* DHCOM DH-iMX6 PDK board configuration
*
* Copyright (C) 2017 Marek Vasut <marex@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DH_IMX6_CONFIG_H
#include <asm/arch/imx-regs.h>
-#include <config_distro_defaults.h>
#include "mx6_common.h"
/*
/* SPL */
#include "imx6_spl.h" /* common IMX6 SPL configuration */
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x11400
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_TARGET "u-boot-with-spl.imx"
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_CMDLINE_EDITING
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
-#define CONFIG_SUPPORT_RAW_INITRD /* bootz raw initrd support */
-#define CONFIG_BOUNCE_BUFFER
#define CONFIG_BZIP2
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M)
/* Bootcounter */
-#define CONFIG_BOOTCOUNT_LIMIT
-#define CONFIG_SYS_BOOTCOUNT_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_BOOTCOUNT_BE
/* FEC ethernet */
-#define CONFIG_MII
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_SYS_I2C_SPEED 100000
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 3
/* SPI Flash Configs */
#ifdef CONFIG_CMD_SF
-#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 25000000
/* UART */
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
-#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
/* USB Configs */
#endif
/* Watchdog */
-#define CONFIG_HW_WATCHDOG
-#define CONFIG_IMX_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_TEXT_BASE 0x17800000
#define CONFIG_LOADADDR 0x12000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#endif
/* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM