+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Embest/Timll DevKit3250 board configuration file
*
* Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_DEVKIT3250_H__
/*
* Memory configurations
*/
-#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_MALLOC_LEN SZ_1M
#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
#define CONFIG_SYS_SDRAM_SIZE SZ_64M
#define CONFIG_SYS_MAX_FLASH_SECT 71
#define CONFIG_SYS_FLASH_BASE EMC_CS0_BASE
#define CONFIG_SYS_FLASH_SIZE SZ_4M
-#define CONFIG_SYS_FLASH_CFI
/*
* NAND controller
*/
-#define CONFIG_NAND_LPC32XX_SLC
#define CONFIG_SYS_NAND_BASE SLC_NAND_BASE
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
* SPL specific defines
*/
/* SPL will be executed at offset 0 */
-#define CONFIG_SPL_TEXT_BASE 0x00000000
/* SPL will use SRAM as stack */
#define CONFIG_SPL_STACK 0x0000FFF8