/* SPL */
/* Defines for SPL */
-#define CONFIG_SPL_MAX_SIZE ((128 << 10) - (CONFIG_SPL_TEXT_BASE - 0x40000000))
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
-#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MALLOC_SIMPLE
-#endif
-
-#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
-#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_SPD_EEPROM 0x4e