Convert CONFIG_USB_MAX_CONTROLLER_COUNT to Kconfig

[platform/kernel/u-boot.git] / include / configs / db-mv784mp-gp.h

diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index 907bd0d..715a6d7 100644 (file)
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -7,46 +7,24 @@
 #define _CONFIG_DB_MV7846MP_GP_H
 
 /*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_DB_784MP_GP             /* Board target name for DDR training */
-
-/*
  * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
  * for DDR ECC byte filling in the SPL before loading the main
  * U-Boot into it.
  */
-#define CONFIG_SYS_TCLK                250000000       /* 250MHz */
 
 /* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MVTWSI
 #define CONFIG_I2C_MVTWSI_BASE0                MVEBU_TWSI_BASE
-#define CONFIG_SYS_I2C_SLAVE           0x0
-#define CONFIG_SYS_I2C_SPEED           100000
 
 /* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
 
 /* Environment in SPI NOR flash */
-#define CONFIG_ENV_OFFSET              (1 << 20) /* 1MiB in */
-#define CONFIG_ENV_SIZE                        (64 << 10) /* 64KiB */
-#define CONFIG_ENV_SECT_SIZE           (64 << 10) /* 64KiB sectors */
 
 #define PHY_ANEG_TIMEOUT       8000    /* PHY needs a longer aneg time */
 
-/* SATA support */
-#define CONFIG_SYS_SATA_MAX_DEVICE     2
-#define CONFIG_LBA48
-
 /* PCIe support */
-#ifndef CONFIG_SPL_BUILD
 #define CONFIG_PCI_SCAN_SHOW
-#endif
 
 /* NAND */
-#define CONFIG_SYS_NAND_ONFI_DETECTION
 
 /*
  * mv-common.h should be defined after CMD configs since it used them
@@ -69,23 +47,8 @@
 
 /* SPL */
 /* Defines for SPL */
-#define CONFIG_SPL_MAX_SIZE            ((128 << 10) - 0x4030)
-
-#define CONFIG_SPL_BSS_START_ADDR      (0x40000000 + (128 << 10))
-#define CONFIG_SPL_BSS_MAX_SIZE                (16 << 10)
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MALLOC_SIMPLE
-#endif
-
-#define CONFIG_SPL_STACK               (0x40000000 + ((192 - 16) << 10))
-#define CONFIG_SPL_BOOTROM_SAVE                (CONFIG_SPL_STACK + 4)
-
-/* SPL related SPI defines */
-#define CONFIG_SYS_U_BOOT_OFFS         CONFIG_SYS_SPI_U_BOOT_OFFS
 
 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
 #define CONFIG_SPD_EEPROM              0x4e
-#define CONFIG_BOARD_ECC_SUPPORT       /* this board supports ECC */
 
 #endif /* _CONFIG_DB_MV7846MP_GP_H */