Merge git://git.denx.de/u-boot-socfpga

[platform/kernel/u-boot.git] / include / configs / db-mv784mp-gp.h

diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index 4a5be61..6ed58ce 100644 (file)
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef _CONFIG_DB_MV7846MP_GP_H
@@ -12,14 +11,11 @@
  */
 #define CONFIG_DB_784MP_GP             /* Board target name for DDR training */
 
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-
 /*
  * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
  * for DDR ECC byte filling in the SPL before loading the main
  * U-Boot into it.
  */
-#define        CONFIG_SYS_TEXT_BASE    0x00800000
 #define CONFIG_SYS_TCLK                250000000       /* 250MHz */
 
 /* I2C */
@@ -33,32 +29,19 @@
 #define CONFIG_EHCI_IS_TDI
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
 
-/* SPI NOR flash default params, used by sf commands */
-#define CONFIG_SF_DEFAULT_SPEED                1000000
-#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_3
-
 /* Environment in SPI NOR flash */
 #define CONFIG_ENV_OFFSET              (1 << 20) /* 1MiB in */
 #define CONFIG_ENV_SIZE                        (64 << 10) /* 64KiB */
 #define CONFIG_ENV_SECT_SIZE           (64 << 10) /* 64KiB sectors */
 
-#define CONFIG_PHY_MARVELL             /* there is a marvell phy */
 #define PHY_ANEG_TIMEOUT       8000    /* PHY needs a longer aneg time */
 
-#define CONFIG_SYS_ALT_MEMTEST
-
 /* SATA support */
 #define CONFIG_SYS_SATA_MAX_DEVICE     2
-#define CONFIG_SATA_MV
-#define CONFIG_LIBATA
 #define CONFIG_LBA48
 
-/* Additional FS support/configuration */
-#define CONFIG_SUPPORT_VFAT
-
 /* PCIe support */
 #ifndef CONFIG_SPL_BUILD
-#define CONFIG_PCI_MVEBU
 #define CONFIG_PCI_SCAN_SHOW
 #endif
 
@@ -87,8 +70,6 @@
 
 /* SPL */
 /* Defines for SPL */
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_TEXT_BASE           0x40004030
 #define CONFIG_SPL_MAX_SIZE            ((128 << 10) - 0x4030)
 
 #define CONFIG_SPL_BSS_START_ADDR      (0x40000000 + (128 << 10))
@@ -102,7 +83,6 @@
 #define CONFIG_SPL_BOOTROM_SAVE                (CONFIG_SPL_STACK + 4)
 
 /* SPL related SPI defines */
-#define CONFIG_SPL_SPI_LOAD
 #define CONFIG_SYS_SPI_U_BOOT_OFFS     0x20000
 #define CONFIG_SYS_U_BOOT_OFFS         CONFIG_SYS_SPI_U_BOOT_OFFS