* (easy to change)
*/
-#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
+#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_CSB472 1 /* on a Cogent CSB472 board */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */
*/
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */
+#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */
/* 32usec min. for LXT971A */
#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*
- * Cache configuration
- *
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
- /* have only 8kB, 16kB is save here */
-#define CFG_CACHELINE_SIZE 32
-
-/*
* Miscellaneous board specific definitions
*
*/