* (easy to change)
*/
-#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
+#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_CSB272 1 /* on a Cogent CSB272 board */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */
*/
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */
+#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */
/* 32usec min. for LXT971A */
#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
* Environment configuration
*
*/
-#define CFG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */
-#undef CFG_ENV_IS_IN_NVRAM
-#undef CFG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */
+#undef CONFIG_ENV_IS_IN_NVRAM
+#undef CONFIG_ENV_IS_IN_EEPROM
/*
* General Memory organization
#define CFG_RAMSTART
#endif
-#if defined(CFG_ENV_IS_IN_FLASH)
-#define CFG_ENV_IN_OWN_SECTOR 1 /* Give Environment own sector */
-#define CFG_ENV_ADDR 0xFFF00000 /* Address of Environment Sector */
-#define CFG_ENV_SIZE 0x00001000 /* Size of Environment */
-#define CFG_ENV_SECT_SIZE 0x00040000 /* Size of Environment Sector */
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+#define CONFIG_ENV_IN_OWN_SECTOR 1 /* Give Environment own sector */
+#define CONFIG_ENV_ADDR 0xFFF00000 /* Address of Environment Sector */
+#define CONFIG_ENV_SIZE 0x00001000 /* Size of Environment */
+#define CONFIG_ENV_SECT_SIZE 0x00040000 /* Size of Environment Sector */
#endif
/*
*
*/
#define CFG_FLASH_CFI 1 /* flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */
#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*
- * Cache configuration
- *
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
- /* have only 8kB, 16kB is save here */
-#define CFG_CACHELINE_SIZE 32
-
-/*
* Miscellaneous board specific definitions
*
*/