Merge branch 'next'

[platform/kernel/u-boot.git] / include / configs / corenet_ds.h

diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 8ad28ad..f6e0b2a 100644 (file)
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -47,15 +47,12 @@
 #define CONFIG_SYS_NUM_CPC             CONFIG_SYS_NUM_DDR_CTLRS
 #define CONFIG_PCIE1                   /* PCIE controller 1 */
 #define CONFIG_PCIE2                   /* PCIE controller 2 */
-#define CONFIG_SYS_PCI_64BIT           /* enable 64-bit PCI resources */
 
 #if defined(CONFIG_SPIFLASH)
 #elif defined(CONFIG_SDCARD)
 #define CONFIG_FSL_FIXED_MMC_LOCATION
 #endif
 
-#define CONFIG_SYS_CLK_FREQ    get_board_sys_clk() /* sysclk for MPC85xx */
-
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
@@ -128,10 +125,6 @@
 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
                                        | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 
-#define CONFIG_SYS_BR1_PRELIM \
-       (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR1_PRELIM  0xf8000ff7
-
 #define PIXIS_BASE             0xffdf0000      /* PIXIS registers */
 #ifdef CONFIG_PHYS_64BIT
 #define PIXIS_BASE_PHYS                0xfffdf0000ull
@@ -139,9 +132,6 @@
 #define PIXIS_BASE_PHYS                PIXIS_BASE
 #endif
 
-#define CONFIG_SYS_BR3_PRELIM  (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR3_PRELIM  0xffffeff7      /* 32KB but only 4k mapped */
-
 #define PIXIS_LBMAP_SWITCH     7
 #define PIXIS_LBMAP_MASK       0xf0
 #define PIXIS_LBMAP_SHIFT      4
@@ -187,21 +177,6 @@
                               | OR_FCM_SCY_1 \
                               | OR_FCM_TRLX \
                               | OR_FCM_EHTR)
-
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
-#else
-#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
-#define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#endif
-#else
-#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 #endif /* CONFIG_NAND_FSL_ELBC */
 
 #define CONFIG_SYS_FLASH_EMPTY_INFO
@@ -414,7 +389,6 @@
 #define CONFIG_HAS_FSL_MPH_USB
 
 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
-#define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #endif