Rename CONFIG_SYS_INIT_RAM_END into CONFIG_SYS_INIT_RAM_SIZE

[platform/kernel/u-boot.git] / include / configs / corenet_ds.h

diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index c021d82..065e89f 100644 (file)
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -86,6 +86,7 @@
 #define CONFIG_SYS_NUM_ADDR_MAP                64      /* number of TLB1 entries */
 #endif
 
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY     /* test POST memory test */
 #define CONFIG_SYS_MEMTEST_START       0x00200000      /* memtest works on */
 #define CONFIG_SYS_MEMTEST_END         0x00400000
 #define CONFIG_SYS_ALT_MEMTEST
@@ -129,68 +130,10 @@
 #define CONFIG_DDR_SPD
 #define CONFIG_FSL_DDR3
 
-#ifdef CONFIG_DDR_SPD
 #define CONFIG_SYS_SPD_BUS_NUM 1
 #define SPD_EEPROM_ADDRESS1    0x51
 #define SPD_EEPROM_ADDRESS2    0x52
-#else
-#define CONFIG_SYS_SDRAM_SIZE          4096
-
-#define CONFIG_SYS_DDR_CS0_BNDS                0x0000003f
-#define CONFIG_SYS_DDR_CS1_BNDS                0x0040007f
-#define CONFIG_SYS_DDR_CS0_CONFIG      0x80014202
-#define CONFIG_SYS_DDR_CS1_CONFIG      0x80014202
-#define CONFIG_SYS_DDR_TIMING_3                0x01031000
-#define CONFIG_SYS_DDR_TIMING_0                0x55440804
-#define CONFIG_SYS_DDR_TIMING_1                0x74713a66
-#define CONFIG_SYS_DDR_TIMING_2                0x0fb8911b
-#define CONFIG_SYS_DDR_MODE_1          0x00421850
-#define CONFIG_SYS_DDR_MODE_2          0x00100000
-#define CONFIG_SYS_DDR_MODE_CTRL       0x00000000
-#define CONFIG_SYS_DDR_INTERVAL                0x10400100
-#define CONFIG_SYS_DDR_DATA_INIT       0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL                0x03000000
-#define CONFIG_SYS_DDR_TIMING_4                0x00220001
-#define CONFIG_SYS_DDR_TIMING_5                0x03401500
-#define CONFIG_SYS_DDR_ZQ_CNTL         0x89080600
-#define CONFIG_SYS_DDR_WRLVL_CNTL      0x8655a608
-#define CONFIG_SYS_DDR_CONTROL         0xc7048000
-#define CONFIG_SYS_DDR_CONTROL2                0x24400011
-#define CONFIG_SYS_DDR_CDR1            0x00000000
-#define CONFIG_SYS_DDR_CDR2            0x00000000
-#define CONFIG_SYS_DDR_ERR_INT_EN      0x0000000d
-#define CONFIG_SYS_DDR_ERR_DIS         0x00000000
-#define CONFIG_SYS_DDR_SBE             0x00010000
-#define CONFIG_SYS_DDR_DEBUG_18                0x40100400
-
-#define CONFIG_SYS_DDR2_CS0_BNDS       0x008000bf
-#define CONFIG_SYS_DDR2_CS1_BNDS       0x00C000ff
-#define CONFIG_SYS_DDR2_CS0_CONFIG     CONFIG_SYS_DDR_CS0_CONFIG
-#define CONFIG_SYS_DDR2_CS1_CONFIG     CONFIG_SYS_DDR_CS1_CONFIG
-#define CONFIG_SYS_DDR2_TIMING_3       CONFIG_SYS_DDR_TIMING_3
-#define CONFIG_SYS_DDR2_TIMING_0       CONFIG_SYS_DDR_TIMING_0
-#define CONFIG_SYS_DDR2_TIMING_1       CONFIG_SYS_DDR_TIMING_1
-#define CONFIG_SYS_DDR2_TIMING_2       CONFIG_SYS_DDR_TIMING_2
-#define CONFIG_SYS_DDR2_MODE_1         CONFIG_SYS_DDR_MODE_1
-#define CONFIG_SYS_DDR2_MODE_2         CONFIG_SYS_DDR_MODE_2
-#define CONFIG_SYS_DDR2_MODE_CTRL      CONFIG_SYS_DDR_MODE_CTRL
-#define CONFIG_SYS_DDR2_INTERVAL       CONFIG_SYS_DDR_INTERVAL
-#define CONFIG_SYS_DDR2_DATA_INIT      CONFIG_SYS_DDR_DATA_INIT
-#define CONFIG_SYS_DDR2_CLK_CTRL       CONFIG_SYS_DDR_CLK_CTRL
-#define CONFIG_SYS_DDR2_TIMING_4       CONFIG_SYS_DDR_TIMING_4
-#define CONFIG_SYS_DDR2_TIMING_5       CONFIG_SYS_DDR_TIMING_5
-#define CONFIG_SYS_DDR2_ZQ_CNTL                CONFIG_SYS_DDR_ZQ_CNTL
-#define CONFIG_SYS_DDR2_WRLVL_CNTL     CONFIG_SYS_DDR_WRLVL_CNTL
-#define CONFIG_SYS_DDR2_CONTROL                CONFIG_SYS_DDR_CONTROL
-#define CONFIG_SYS_DDR2_CONTROL2       CONFIG_SYS_DDR_CONTROL2
-#define CONFIG_SYS_DDR2_CDR1           CONFIG_SYS_DDR_CDR1
-#define CONFIG_SYS_DDR2_CDR2           CONFIG_SYS_DDR_CDR2
-#define CONFIG_SYS_DDR2_ERR_INT_EN     CONFIG_SYS_DDR_ERR_INT_EN
-#define CONFIG_SYS_DDR2_ERR_DIS                CONFIG_SYS_DDR_ERR_DIS
-#define CONFIG_SYS_DDR2_SBE            CONFIG_SYS_DDR_SBE
-#define CONFIG_SYS_DDR2_DEBUG_18       CONFIG_SYS_DDR_DEBUG_18
-
-#endif
+#define CONFIG_SYS_SDRAM_SIZE  4096    /* for fixed parameter use */
 
 /*
  * Local Bus Definitions
@@ -268,10 +211,10 @@
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 #endif
-#define CONFIG_SYS_INIT_RAM_END                0x00004000      /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE               0x00004000      /* Size of used area in RAM */
 
-#define CONFIG_SYS_GBL_DATA_SIZE       128     /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_SIZE       256     /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN         (512 * 1024)