*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation,
+ * Foundation,
*/
/*
* File: cmi_mpc5xx.h
- *
- * Discription: Config header file for cmi
+ *
+ * Discription: Config header file for cmi
* board using an MPC5xx CPU
*
*/
#define CONFIG_BAUDRATE 57600
-#define CONFIG_COMMANDS (CFG_CMD_MEMORY | CFG_CMD_LOADB | CFG_CMD_REGINFO | \
- CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_ASKENV | \
- CFG_CMD_BDI | CFG_CMD_CONSOLE | CFG_CMD_ENV | CFG_CMD_RUN | \
- CFG_CMD_IMI)
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_NET /* disabeled - causes compile errors */
+
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_IMI
+
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#define CONFIG_WATCHDOG /* turn on platform specific watchdog */
-#define CONFIG_STATUS_LED 1 /* Enable status led */
+#define CONFIG_STATUS_LED 1 /* Enable status led */
#define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */
/*
- * Miscellaneous configurable options
+ * Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
/*
* Definitions for initial stack pointer and data area
*/
-#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */
+#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */
#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */
#define CFG_GBL_DATA_SIZE 64 /* Size in bytes reserved for initial global data */
#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */
/*-----------------------------------------------------------------------
- * FLASH organization
+ * FLASH organization
*-----------------------------------------------------------------------
- *
+ *
*/
#define CFG_MAX_FLASH_BANKS 1 /* Max number of memory banks */
#define CFG_ENV_IS_IN_FLASH 1
#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */
-#define CFG_ENV_SIZE 0x00010000 /* Set whole sector as env */
+#define CFG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */
+#define CFG_ENV_SIZE 0x00010000 /* Set whole sector as env */
+#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
#endif
/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control
+ * SYPCR - System Protection Control
* SYPCR can only be written once after reset!
*-----------------------------------------------------------------------
* SW Watchdog freeze
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWP)
+ SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register
*-----------------------------------------------------------------------
* Set all bits to 40 Mhz
- *
+ *
*/
#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */
#define CFG_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0)
-
+
/*-----------------------------------------------------------------------
* UMCR - UIMB Module Configuration Register
*-----------------------------------------------------------------------
- *
+ *
*/
#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */
/*-----------------------------------------------------------------------
* ICTRL - I-Bus Support Control Register
*/
-#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */
+#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */
/*-----------------------------------------------------------------------
* USIU - Memory Controller Register
- *-----------------------------------------------------------------------
+ *-----------------------------------------------------------------------
*/
-#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_V | BR_BI | BR_PS_16)
+#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_V | BR_BI | BR_PS_16)
#define CFG_OR0_PRELIM (OR_ADDR_MK_FF | OR_SCY_3)
#define CFG_BR1_PRELIM (ANYBUS_BASE)
#define CFG_OR1_PRELIM (OR_ADDR_MK_FFFF | OR_SCY_1 | OR_ETHR)
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* We don't realign the flash */
/*-----------------------------------------------------------------------
- * DER - Timer Decrementer
+ * DER - Timer Decrementer
*-----------------------------------------------------------------------
* Initialise to zero
*/
projects / platform / kernel / u-boot.git / blobdiff