/* Machine config */
#define CONFIG_SYS_LITTLE_ENDIAN
-#define CONFIG_MACH_TYPE 4273
/* MMC */
#define CONFIG_SYS_FSL_USDHC_NUM 3
#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_MEMTEST_START 0x10000000
-#define CONFIG_SYS_MEMTEST_END 0x10010000
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* Serial console */
-#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART4_BASE
-#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
/* Environment */
-#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-#define CONFIG_ENV_SIZE (8 * 1024)
-#define CONFIG_ENV_OFFSET (768 * 1024)
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
"initrd_high=0xffffffff\0" \
"fdt_addr_r=0x18000000\0" \
"ramdisk_addr_r=0x13000000\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"fdtfile=undefined\0" \
"stdin=serial,usbkbd\0" \
- "stdout=serial,vga\0" \
- "stderr=serial,vga\0" \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0" \
"panel=HDMI\0" \
"autoload=no\0" \
"uImage=uImage-cm-fx6\0" \
/* NAND */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_ONFI_DETECTION
/* APBH DMA is required for NAND support */
#endif
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_FEC_XCV_TYPE RGMII
#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_PHY_ATHEROS
#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_ARP_TIMEOUT 200UL
#define CONFIG_NET_RETRY_COUNT 5
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_MXC_I2C3_SPEED 400000
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_I2C_EEPROM_BUS 2
-
/* SATA */
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_LBA48
/* Boot */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
-#define CONFIG_SERIAL_TAG
/* misc */
-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
/* SPL */
#include "imx6_spl.h"
/* Display */
#define CONFIG_IMX_HDMI
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SPLASH_SOURCE
-#define CONFIG_VIDEO_BMP_RLE8
-
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
/* EEPROM */
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-#define CONFIG_SYS_EEPROM_SIZE 256
#endif /* __CONFIG_CM_FX6_H */