#define CONFIG_SYS_FLASH_BASE_PHYS (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \
(u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
-#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 16k */
+#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */
#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000
*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+#define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */
#define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */
#else
#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
+#define CONFIG_SYS_NOR_CS 3 /* NOR chip connected to CSx */
#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
#endif
* NAND-FLASH related
*----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+/* I2C bootstrap EEPROM */
+#if defined(CONFIG_ARCHES)
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54
+#else
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
+#endif
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
+#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
+
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
#define CONFIG_DTT_AD7414 1 /* use AD7414 */
/*
* Commands additional to the ones defined in amcc-common.h
*/
+#define CONFIG_CMD_CHIP_CONFIG
#if defined(CONFIG_ARCHES)
#define CONFIG_CMD_DTT
#define CONFIG_CMD_PCI
#define CONFIG_CMD_FAT
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SATA
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB
#endif /* CONFIG_ARCHES */
#endif /* CONFIG_460GT */
+/*
+ * SATA driver setup
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_SATA_DWC
+#define CONFIG_LIBATA
+#define SATA_BASE_ADDR 0xe20d1000 /* PPC460EX SATA Base Address */
+#define SATA_DMA_REG_ADDR 0xe20d0800 /* PPC460EX SATA Base Address */
+#define CONFIG_SYS_SATA_MAX_DEVICE 1 /* SATA MAX DEVICE */
+/* Convert sectorsize to wordsize */
+#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
+#endif
+
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FPGA_BASE | 0x3a000) /* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/
#endif /* !defined(CONFIG_ARCHES) */
-#define CONFIG_SYS_EBC_CFG 0xB8400000 /* EBC0_CFG */
+#define CONFIG_SYS_EBC_CFG 0xbfc00000
/*
* Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO