Merge branch 'master' into next

[platform/kernel/u-boot.git] / include / configs / canyonlands.h

diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index 48c5198..ac9b3c5 100644 (file)
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -330,6 +330,15 @@
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS      3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  10
 
+/* I2C bootstrap EEPROM */
+#if defined(CONFIG_ARCHES)
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR      0x54
+#else
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR      0x52
+#endif
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET    0
+#define CONFIG_4xx_CONFIG_BLOCKSIZE            16
+
 /* I2C SYSMON (LM75, AD7414 is almost compatible)                      */
 #define CONFIG_DTT_LM75                1               /* ON Semi's LM75       */
 #define CONFIG_DTT_AD7414      1               /* use AD7414           */
@@ -442,6 +451,7 @@
 /*
  * Commands additional to the ones defined in amcc-common.h
  */
+#define CONFIG_CMD_CHIP_CONFIG
 #if defined(CONFIG_ARCHES)
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_PCI
@@ -453,6 +463,7 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_PCI
+#define CONFIG_CMD_SATA
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_SNTP
 #define CONFIG_CMD_USB
@@ -518,6 +529,19 @@
 #endif /* CONFIG_ARCHES */
 #endif /* CONFIG_460GT */
 
+/*
+ * SATA driver setup
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_SATA_DWC
+#define CONFIG_LIBATA
+#define SATA_BASE_ADDR         0xe20d1000      /* PPC460EX SATA Base Address */
+#define SATA_DMA_REG_ADDR      0xe20d0800      /* PPC460EX SATA Base Address */
+#define CONFIG_SYS_SATA_MAX_DEVICE     1       /* SATA MAX DEVICE */
+/* Convert sectorsize to wordsize */
+#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
+#endif
+
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  *----------------------------------------------------------------------*/
@@ -569,7 +593,7 @@
 #define CONFIG_SYS_EBC_PB1CR           (CONFIG_SYS_FPGA_BASE | 0x3a000) /* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/
 #endif /* !defined(CONFIG_ARCHES) */
 
-#define CONFIG_SYS_EBC_CFG             0xB8400000              /*  EBC0_CFG */
+#define CONFIG_SYS_EBC_CFG             0xbfc00000
 
 /*
  * Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO