Rename CONFIG_EHCI_IS_TDI to CONFIG_USB_EHCI_IS_TDI

[platform/kernel/u-boot.git] / include / configs / bur_am335x_common.h

diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h
index 37d6aa5..9b2e8b5 100644 (file)
--- a/include/configs/bur_am335x_common.h
+++ b/include/configs/bur_am335x_common.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * bur_am335x_common.h
  *
@@ -5,13 +6,21 @@
  *
  * Copyright (C) 2016 Hannes Schmelzer <oe5hpm@oevsv.at> -
  * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
- *
- * SPDX-License-Identifier:        GPL-2.0+
  */
 
 #ifndef __BUR_AM335X_COMMON_H__
 #define __BUR_AM335X_COMMON_H__
 /* ------------------------------------------------------------------------- */
+
+/* legacy #defines for non DM bur-board */
+#ifndef CONFIG_DM
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    (-4)
+#define CONFIG_SYS_NS16550_CLK         (48000000)
+#define CONFIG_SYS_NS16550_COM1                0x44e09000
+
+#endif /* CONFIG_DM */
+
 #define CONFIG_MAX_RAM_BANK_SIZE       (1024 << 20)    /* 1GB */
 
 /* Timer information */
@@ -21,16 +30,6 @@
 
 #include <asm/arch/omap.h>
 
-/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE    (-4)
-#define CONFIG_SYS_NS16550_CLK         48000000
-#define CONFIG_SYS_NS16550_COM1                0x44e09000      /* UART0 */
-
-/* Network defines */
-#define CONFIG_MII                     /* Required in net/eth.c */
-#define CONFIG_PHY_NATSEMI
-
 /*
  * SPL related defines.  The Public RAM memory map the ROM defines the
  * area between 0x402F0400 and 0x4030B800 as a download area and
@@ -39,7 +38,6 @@
  * Y-MODEM to load u-boot.img, when booted over UART.  We must also include
  * the scratch space that U-Boot uses in SRAM.
  */
-#define CONFIG_SPL_TEXT_BASE           0x402F0400
 #define CONFIG_SPL_MAX_SIZE            (SRAM_SCRATCH_SPACE_ADDR - \
                                         CONFIG_SPL_TEXT_BASE)
 
@@ -47,28 +45,16 @@
  * Since SPL did pll and ddr initialization for us,
  * we don't need to do it twice.
  */
-#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif /* !CONFIG_SPL_BUILD, ... */
-/*
- * Our DDR memory always starts at 0x80000000 and U-Boot shall have
- * relocated itself to higher in memory by the time this value is used.
- */
-#define CONFIG_SYS_LOAD_ADDR           0x80000000
 /*
  * ----------------------------------------------------------------------------
  * DDR information.  We say (for simplicity) that we have 1 bank,
  * always, even when we have more.  We always start at 0x80000000,
  * and we place the initial stack pointer in our SRAM.
  */
-#define CONFIG_NR_DRAM_BANKS           1
 #define CONFIG_SYS_SDRAM_BASE          0x80000000
 #define CONFIG_SYS_INIT_SP_ADDR                (NON_SECURE_SRAM_END - \
                                        GENERATED_GBL_DATA_SIZE)
 
-/* I2C */
-#define CONFIG_SYS_I2C
-
 /*
  * Our platforms make use of SPL to initalize the hardware (primarily
  * memory) enough for full U-Boot to be loaded.  We also support Falcon