Merge branch 'master' of git://git.denx.de/u-boot-imx
[platform/kernel/u-boot.git] / include / configs / bf537-pnav.h
index cf40d06..da4f2f2 100644 (file)
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf537-0.2
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
 
 
@@ -52,7 +51,7 @@
 #define CONFIG_EBIU_AMBCTL0_VAL        0x7BB033B0
 #define CONFIG_EBIU_AMBCTL1_VAL        0xFFC27BB0
 
-#define CONFIG_SYS_MONITOR_LEN         (256 * 1024)
+#define CONFIG_SYS_MONITOR_LEN         (512 * 1024)
 #define CONFIG_SYS_MALLOC_LEN          (128 * 1024)
 
 
  * it linked after the configuration sector.
  */
 # define LDS_BOARD_TEXT \
-       arch/blackfin/cpu/traps.o               (.text .text.*); \
-       arch/blackfin/cpu/interrupt.o   (.text .text.*); \
-       arch/blackfin/cpu/serial.o              (.text .text.*); \
-       common/dlmalloc.o               (.text .text.*); \
-       lib/crc32.o             (.text .text.*); \
+       arch/blackfin/lib/libblackfin.o (.text*); \
+       arch/blackfin/cpu/libblackfin.o (.text*); \
        . = DEFINED(env_offset) ? env_offset : .; \
-       common/env_embedded.o           (.text .text.*);
+       common/env_embedded.o (.text*);
 #endif
 
 
 
 #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
 #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
-#define BFIN_NAND_READY     PF12
 #define BFIN_NAND_WRITE(addr, cmd) \
        do { \
                bfin_write8(addr, cmd); \
 
 #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_DEV_READY(chip)      (bfin_read_PORTHIO() & BFIN_NAND_READY)
-#define NAND_PLAT_INIT() \
-       do { \
-               bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~BFIN_NAND_READY); \
-               bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() & ~BFIN_NAND_READY); \
-               bfin_write_PORTHIO_INEN(bfin_read_PORTHIO_INEN() | BFIN_NAND_READY); \
-       } while (0)
+#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF12
 
 
 /*
  */
 #define CONFIG_BFIN_TWI_I2C    1
 #define CONFIG_HARD_I2C                1
-#define CONFIG_SYS_I2C_SPEED           50000
-#define CONFIG_SYS_I2C_SLAVE           0
 
 
 /*