#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB033B0
#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
#define ADI_CMDS_NETWORK 1
#define CONFIG_BFIN_MAC
#define CONFIG_RMII
-#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_HOSTNAME bf537-pnav
/* Uncomment next line to use fixed MAC address */
*/
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
-#define CONFIG_SF_DEFAULT_HZ 30000000
+#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
* Env Storage Settings
*/
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
-#define ENV_IS_EMBEDDED_CUSTOM
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x4000
#else
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- cpu/blackfin/traps.o (.text .text.*); \
- cpu/blackfin/interrupt.o (.text .text.*); \
- cpu/blackfin/serial.o (.text .text.*); \
- common/dlmalloc.o (.text .text.*); \
- lib_generic/crc32.o (.text .text.*); \
+ arch/blackfin/lib/libblackfin.o (.text*); \
+ arch/blackfin/cpu/libblackfin.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
- common/env_embedded.o (.text .text.*);
+ common/env_embedded.o (.text*);
#endif
#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
-#define BFIN_NAND_READY PF12
#define BFIN_NAND_WRITE(addr, cmd) \
do { \
bfin_write8(addr, cmd); \
#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_DEV_READY(chip) (bfin_read_PORTHIO() & BFIN_NAND_READY)
-#define NAND_PLAT_INIT() \
- do { \
- bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~BFIN_NAND_READY); \
- bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() & ~BFIN_NAND_READY); \
- bfin_write_PORTHIO_INEN(bfin_read_PORTHIO_INEN() | BFIN_NAND_READY); \
- } while (0)
+#define NAND_PLAT_GPIO_DEV_READY GPIO_PF12
/*
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0
/*