/*
* Processor Settings
*/
+#define CONFIG_BFIN_CPU bf536-0.3
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 16384000
-/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
-/* 1 = CLKIN / 2 */
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
-/* 1 = bypass PLL */
+/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 3
-#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000)
+#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000)
/*
#define ADI_CMDS_NETWORK 1
#define CONFIG_BFIN_MAC 1
#define CONFIG_NETCONSOLE 1
-#define CONFIG_NET_MULTI 1
#define CONFIG_HOSTNAME brettl2
#define CONFIG_IPADDR 192.168.233.224
#define CONFIG_GATEWAYIP 192.168.233.1
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
- arch/blackfin/cpu/traps.o (.text .text.*); \
- arch/blackfin/cpu/interrupt.o (.text .text.*); \
- arch/blackfin/cpu/serial.o (.text .text.*); \
- common/dlmalloc.o (.text .text.*); \
- lib/crc32.o (.text .text.*); \
- . = DEFINED(env_offset) ? env_offset : .; \
- common/env_embedded.o (.text .text.*);
+ arch/blackfin/lib/libblackfin.o (.text*); \
+ arch/blackfin/cpu/libblackfin.o (.text*); \
+ . = DEFINED(env_offset) ? env_offset : .; \
+ common/env_embedded.o (.text*);
#endif