Change all '$(...)' variable references into '${...}'

[platform/kernel/u-boot.git] / include / configs / atc.h

diff --git a/include/configs/atc.h b/include/configs/atc.h
index 4f30847..bf6c170 100644 (file)
--- a/include/configs/atc.h
+++ b/include/configs/atc.h
@@ -35,6 +35,7 @@
 
 #define CONFIG_MPC8260         1       /* This is an MPC8260 CPU               */
 #define CONFIG_ATC             1       /* ...on a ATC board    */
+#define CONFIG_CPM2            1       /* Has a CPM2 */
 
 /*
  * select serial console configuration
@@ -112,8 +113,8 @@
 #define CONFIG_BOOTCOMMAND                                             \
        "bootp;"                                                        \
        "setenv bootargs root=/dev/nfs rw "                             \
-       "nfsroot=$(serverip):$(rootpath) "                              \
-       "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"\
+       "nfsroot=${serverip}:${rootpath} "                              \
+       "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\
        "bootm"
 
 /*-----------------------------------------------------------------------
@@ -129,7 +130,10 @@
                                 CFG_CMD_EEPROM | \
                                 CFG_CMD_PCI | \
                                 CFG_CMD_PCMCIA | \
+                                CFG_CMD_DATE | \
                                 CFG_CMD_IDE)
+
+
 #define CONFIG_DOS_PARTITION
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@@ -168,6 +172,14 @@
 
 #define CONFIG_SPI
 
+#define CONFIG_RTC_DS12887
+
+#define RTC_BASE_ADDR          0xF5000000
+#define RTC_PORT_ADDR          RTC_BASE_ADDR + 0x800
+#define RTC_PORT_DATA          RTC_BASE_ADDR + 0x808
+
+#define CONFIG_MISC_INIT_R
+
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
@@ -179,8 +191,6 @@
  * Flash configuration
  */
 
-#define CFG_BOOTROM_BASE       0xFF800000
-#define CFG_BOOTROM_SIZE       0x00080000
 #define CFG_FLASH_BASE         0xFF000000
 #define CFG_FLASH_SIZE         0x00800000
 
@@ -203,7 +213,7 @@
  * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
  */
 #define CFG_HRCW_MASTER                (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
-                                HRCW_BPS10 | HRCW_DPPC10 |\
+                                HRCW_BPS10 |\
                                 HRCW_APPC10)
 
 /* no slaves so just fill with zeros */
@@ -248,6 +258,7 @@
 
 #define        CONFIG_PCI
 #define        CONFIG_PCI_PNP
+#define        CFG_PCI_MSTR_IO_BUS     0x00000000      /* PCI base   */
 
 #if 1
 /* environment is in Flash */
@@ -289,7 +300,7 @@
  * HID1 has only read-only information - nothing to set.
  */
 #define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
-                         HID0_DCI|HID0_IFEM|HID0_ABE)
+                        HID0_DCI|HID0_IFEM|HID0_ABE)
 #define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 #define CFG_HID2        0
 
@@ -311,7 +322,7 @@
  * SIUMCR - SIU Module Configuration                             4-31
  *-----------------------------------------------------------------------
  */
-#define CFG_SIUMCR      (SIUMCR_BBD|SIUMCR_DPPC10|SIUMCR_APPC10|\
+#define CFG_SIUMCR      (SIUMCR_BBD|SIUMCR_APPC10|\
                         SIUMCR_CS10PC00|SIUMCR_BCTLC10)
 
 /*-----------------------------------------------------------------------
@@ -322,10 +333,10 @@
  */
 #if defined(CONFIG_WATCHDOG)
 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-                         SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+                        SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 #else
 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-                         SYPCR_SWRI|SYPCR_SWP)
+                        SYPCR_SWRI|SYPCR_SWP)
 #endif /* CONFIG_WATCHDOG */
 
 /*-----------------------------------------------------------------------
@@ -427,30 +438,37 @@
 /* Bank 0 - FLASH
  */
 #define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
-                         BRx_PS_16                      |\
-                         BRx_MS_GPCM_P                  |\
-                         BRx_V)
+                        BRx_PS_16                      |\
+                        BRx_MS_GPCM_P                  |\
+                        BRx_V)
 
 #define CFG_OR0_PRELIM  (P2SZ_TO_AM(CFG_FLASH_SIZE)     |\
-                         ORxG_CSNT                      |\
-                         ORxG_ACS_DIV1                  |\
-                         ORxG_SCY_3_CLK                 |\
-                         ORxU_EHTR_8IDLE)
+                        ORxG_CSNT                      |\
+                        ORxG_ACS_DIV1                  |\
+                        ORxG_SCY_3_CLK                 |\
+                        ORxU_EHTR_8IDLE)
 
 
 /* Bank 2 - 60x bus SDRAM
  */
 #ifndef CFG_RAMBOOT
 #define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
-                         BRx_PS_64                      |\
-                         BRx_MS_SDRAM_P                 |\
-                         BRx_V)
+                        BRx_PS_64                      |\
+                        BRx_MS_SDRAM_P                 |\
+                        BRx_V)
 
 #define CFG_OR2_PRELIM  CFG_OR2_8COL
 
 #define CFG_PSDMR       CFG_PSDMR_8COL
 #endif /* CFG_RAMBOOT */
 
+#define CFG_BR4_PRELIM  ((RTC_BASE_ADDR & BRx_BA_MSK)   |\
+                        BRx_PS_8                       |\
+                        BRx_MS_UPMA                    |\
+                        BRx_V)
+
+#define CFG_OR4_PRELIM  (ORxU_AM_MSK | ORxU_BI)
+
 /*-----------------------------------------------------------------------
  * PCMCIA stuff
  *-----------------------------------------------------------------------