#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_ATC 1 /* ...on a ATC board */
+#define CONFIG_CPM2 1 /* Has a CPM2 */
/*
* select serial console configuration
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- *
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
#undef CONFIG_ETHER_NONE /* define if ether on something else */
#define CONFIG_BOOTCOMMAND \
"bootp;" \
"setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"\
+ "nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\
"bootm"
/*-----------------------------------------------------------------------
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_EEPROM)
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCMCIA
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_IDE
+
+
+#define CONFIG_DOS_PARTITION
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
+
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_SPI
+#define CONFIG_RTC_DS12887
+
+#define RTC_BASE_ADDR 0xF5000000
+#define RTC_PORT_ADDR RTC_BASE_ADDR + 0x800
+#define RTC_PORT_DATA RTC_BASE_ADDR + 0x808
+
+#define CONFIG_MISC_INIT_R
+
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* Flash configuration
*/
-#define CFG_BOOTROM_BASE 0xFF800000
-#define CFG_BOOTROM_SIZE 0x00080000
#define CFG_FLASH_BASE 0xFF000000
#define CFG_FLASH_SIZE 0x00800000
* HRCW_DPPCxx requires you to also change CFG_SIUMCR.
*/
#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
- HRCW_BPS10 | HRCW_DPPC10 |\
+ HRCW_BPS10 |\
HRCW_APPC10)
/* no slaves so just fill with zeros */
# define CFG_RAMBOOT
#endif
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CFG_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
+
#if 1
/* environment is in Flash */
#define CFG_ENV_IS_IN_FLASH 1
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
* HID1 has only read-only information - nothing to set.
*/
#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\
- HID0_DCI|HID0_IFEM|HID0_ABE)
+ HID0_DCI|HID0_IFEM|HID0_ABE)
#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
#define CFG_HID2 0
* SIUMCR - SIU Module Configuration 4-31
*-----------------------------------------------------------------------
*/
-#define CFG_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC10|SIUMCR_APPC10|\
+#define CFG_SIUMCR (SIUMCR_BBD|SIUMCR_APPC10|\
SIUMCR_CS10PC00|SIUMCR_BCTLC10)
/*-----------------------------------------------------------------------
*/
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+ SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
#else
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP)
+ SYPCR_SWRI|SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */
/*-----------------------------------------------------------------------
*/
#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\
ORxS_BPD_4 |\
- ORxS_ROWST_PBI0_A10 |\
- ORxS_NUMR_11)
+ ORxS_ROWST_PBI1_A7 |\
+ ORxS_NUMR_12)
-#define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
- PSDMR_BSMA_A16_A18 |\
- PSDMR_SDA10_PBI0_A10 |\
+#define CFG_PSDMR_8COL (PSDMR_PBI |\
+ PSDMR_SDAM_A15_IS_A5 |\
+ PSDMR_BSMA_A15_A17 |\
+ PSDMR_SDA10_PBI1_A7 |\
PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_2W |\
- PSDMR_ACTTORW_1W |\
+ PSDMR_PRETOACT_3W |\
+ PSDMR_ACTTORW_2W |\
PSDMR_LDOTOPRE_1C |\
PSDMR_WRC_1C |\
PSDMR_CL_2)
*/
#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\
ORxS_BPD_4 |\
- ORxS_ROWST_PBI0_A7 |\
- ORxS_NUMR_13)
+ ORxS_ROWST_PBI1_A6 |\
+ ORxS_NUMR_12)
-#define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
- PSDMR_BSMA_A13_A15 |\
- PSDMR_SDA10_PBI0_A9 |\
+#define CFG_PSDMR_9COL (PSDMR_PBI |\
+ PSDMR_SDAM_A16_IS_A5 |\
+ PSDMR_BSMA_A15_A17 |\
+ PSDMR_SDA10_PBI1_A6 |\
PSDMR_RFRC_7_CLK |\
- PSDMR_PRETOACT_2W |\
- PSDMR_ACTTORW_1W |\
+ PSDMR_PRETOACT_3W |\
+ PSDMR_ACTTORW_2W |\
PSDMR_LDOTOPRE_1C |\
PSDMR_WRC_1C |\
PSDMR_CL_2)
/* Bank 0 - FLASH
*/
#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
- BRx_PS_16 |\
- BRx_MS_GPCM_P |\
- BRx_V)
+ BRx_PS_16 |\
+ BRx_MS_GPCM_P |\
+ BRx_V)
#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_3_CLK |\
- ORxU_EHTR_8IDLE)
+ ORxG_CSNT |\
+ ORxG_ACS_DIV1 |\
+ ORxG_SCY_3_CLK |\
+ ORxU_EHTR_8IDLE)
/* Bank 2 - 60x bus SDRAM
*/
#ifndef CFG_RAMBOOT
#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_SDRAM_P |\
- BRx_V)
+ BRx_PS_64 |\
+ BRx_MS_SDRAM_P |\
+ BRx_V)
#define CFG_OR2_PRELIM CFG_OR2_8COL
#define CFG_PSDMR CFG_PSDMR_8COL
#endif /* CFG_RAMBOOT */
+#define CFG_BR4_PRELIM ((RTC_BASE_ADDR & BRx_BA_MSK) |\
+ BRx_PS_8 |\
+ BRx_MS_UPMA |\
+ BRx_V)
+
+#define CFG_OR4_PRELIM (ORxU_AM_MSK | ORxU_BI)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_I82365
+
+#define CFG_PCMCIA_MEM_ADDR 0x81000000
+#define CFG_PCMCIA_MEM_SIZE 0x1000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
+
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
+#undef CONFIG_IDE_RESET /* reset for ide not supported */
+
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
+
+#define CFG_ATA_IDE0_OFFSET 0x0000
+
+#define CFG_ATA_BASE_ADDR 0xa0000000
+
+/* Offset for data I/O */
+#define CFG_ATA_DATA_OFFSET 0x100
+
+/* Offset for normal register accesses */
+#define CFG_ATA_REG_OFFSET 0x100
+
+/* Offset for alternate registers */
+#define CFG_ATA_ALT_OFFSET 0x108
+
#endif /* __CONFIG_H */
projects / platform / kernel / u-boot.git / blobdiff