#ifndef __CONFIG_H
#define __CONFIG_H
-#undef DEBUG
-
/*
* High Level Configuration Options
* (easy to change)
#define CONFIG_ASSABET 1 /* on an Intel Assabet Board */
#undef CONFIG_USE_IRQ
+/* we will never enable dcache, because we have to setup MMU first */
+#define CONFIG_SYS_NO_DCACHE
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
/*
* Size of malloc() pool
*/
-#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
-#define CFG_GBL_DATA_SIZE 128 /* size rsrvd for initial data */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
/*
* Hardware drivers
*/
-#define CONFIG_DRIVER_LAN91C96 /* we have an SMC9194 on-board */
+#define CONFIG_NET_MULTI
+#define CONFIG_LAN91C96 /* we have an SMC9194 on-board */
#define CONFIG_LAN91C96_BASE 0x18000000
/*
* select serial console configuration
*/
+#define CONFIG_SA1100_SERIAL
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on Intel Assabet */
/* allow to overwrite serial and ethaddr */
#define CONFIG_BAUDRATE 115200
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP)
-#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "console=ttySA0,115200n8 root=/dev/nfs ip=bootp"
#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm"
-#define CFG_AUTOLOAD "n" /* No autoload */
+#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
* Miscellaneous configurable options
*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "Intel Assabet # " /* Monitor Command Prompt */
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-
-#define CFG_MEMTEST_START 0xc0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "Intel Assabet # " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#undef CFG_CLKS_IN_HZ
+#define CONFIG_SYS_MEMTEST_START 0xc0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */
-#define CFG_LOAD_ADDR 0xc0000000 /* default load address */
+#define CONFIG_SYS_LOAD_ADDR 0xc0000000 /* default load address */
-#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
-#define CFG_CPUSPEED 0x0a /* set core clock to 206MHz */
+#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_CPUSPEED 0x0a /* set core clock to 206MHz */
/* valid baudrates */
-#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*-----------------------------------------------------------------------
* Stack sizes
#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */
#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
-#define CFG_MONITOR_BASE TEXT_BASE
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */
-#if CFG_MONITOR_BASE < CFG_FLASH_BASE
-#define CFG_RAMSTART
+#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_RAMSTART
#endif
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
-#define CFG_FLASH_BASE PHYS_FLASH_1
-#define CFG_FLASH_SIZE PHYS_FLASH_SIZE
-#define CFG_FLASH_CFI 1 /* flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
-#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */
-#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
-#define CFG_MAX_FLASH_SECT 128 /* max # of sectors on one chip */
-#undef CFG_FLASH_PROTECTION
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
-
-#define CFG_ENV_IS_IN_FLASH 1
-
-#if defined(CFG_ENV_IS_IN_FLASH)
-#define CFG_ENV_IN_OWN_SECTOR 1
-#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
-#define CFG_ENV_SIZE PHYS_FLASH_SECT_SIZE
-#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_SIZE PHYS_FLASH_SIZE
+#define CONFIG_SYS_FLASH_CFI 1 /* flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */
+#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
+#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max # of sectors on one chip */
+#undef CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_ENV_IS_IN_FLASH 1
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+#define CONFIG_ENV_IN_OWN_SECTOR 1
+#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
+#define CONFIG_ENV_SIZE PHYS_FLASH_SECT_SIZE
+#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
#endif
#endif /* __CONFIG_H */