#define CONFIG_BOARD_LATE_INIT
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
/* SPL defines. */
#define CONFIG_SPL_TEXT_BASE CONFIG_ISW_ENTRY_ADDR
-#define CONFIG_SPL_MAX_SIZE (NON_SECURE_SRAM_END - \
- CONFIG_PUB_ROM_DATA_SIZE - \
- CONFIG_SPL_TEXT_BASE)
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
(128 << 20))
#define CONFIG_SPL_POWER_SUPPORT
/* Enabling L2 Cache */
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0x48242000
-#define CONFIG_SYS_CACHELINE_SIZE 32
/*
* Since SPL did pll and ddr initialization for us,
#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1
-#define CONFIG_USB_HOST
-#define CONFIG_USB_XHCI
-#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_XHCI_OMAP
-#define CONFIG_USB_STORAGE
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_OMAP_USB_PHY