configs: move CONFIG_SPL_TEXT_BASE to Kconfig

[platform/kernel/u-boot.git] / include / configs / am3517_crane.h

diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index ce9d4f8..2c51026 100644 (file)
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * am3517_crane.h - Default configuration for AM3517 CraneBoard.
  *
@@ -6,8 +7,6 @@
  * Based on include/configs/am3517evm.h
  *
  * Copyright (C) 2011 Mistral Solutions pvt Ltd
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __CONFIG_H
@@ -16,7 +15,6 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_EMIF4   /* The chip has EMIF4 controller */
 
 #include <asm/arch/cpu.h>              /* get chip and board defs */
 #include <asm/arch/omap.h>
@@ -25,8 +23,6 @@
 #define V_OSCK                 26000000        /* Clock output from T2 */
 #define V_SCLK                 (V_OSCK >> 1)
 
-#define CONFIG_MISC_INIT_R
-
 #define CONFIG_CMDLINE_TAG             1       /* enable passing of ATAGs */
 #define CONFIG_SETUP_MEMORY_TAGS       1
 #define CONFIG_INITRD_TAG              1
@@ -59,9 +55,7 @@
 /*
  * select serial console configuration
  */
-#define CONFIG_CONS_INDEX              3
 #define CONFIG_SYS_NS16550_COM3                OMAP34XX_UART3
-#define CONFIG_SERIAL3                 3       /* UART3 on CRANEBOARD */
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
@@ -73,8 +67,6 @@
  * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
  * Enable CONFIG_USB_MUSB_UDC for Device functionalities.
  */
-#define CONFIG_USB_AM35X               1
-#define CONFIG_USB_MUSB_HCD                    1
 
 #ifdef CONFIG_USB_AM35X
 
@@ -100,14 +92,10 @@
 #endif /* CONFIG_USB_AM35X */
 
 #define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED    100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE    1
 
 /*
  * Board NAND Info.
  */
-#define CONFIG_SYS_NAND_ADDR           NAND_BASE       /* physical address */
-                                                       /* to access nand */
 #define CONFIG_SYS_NAND_BASE           NAND_BASE       /* physical address */
                                                        /* to access */
                                                        /* nand at CS0 */
@@ -160,16 +148,12 @@
                "fi; " \
        "else run nandboot; fi"
 
-#define CONFIG_AUTO_COMPLETE   1
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_LONGHELP            /* undef to save memory */
 #define CONFIG_SYS_CBSIZE              512     /* Console I/O Buffer Size */
 #define CONFIG_SYS_MAXARGS             32      /* max number of command */
                                                /* args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE            (CONFIG_SYS_CBSIZE)
 /* memtest works on */
 #define CONFIG_SYS_MEMTEST_START       (OMAP34XX_SDRC_CS0)
 #define CONFIG_SYS_MEMTEST_END         (OMAP34XX_SDRC_CS0 + \
@@ -189,7 +173,6 @@
 /*-----------------------------------------------------------------------
  * Physical Memory Map
  */
-#define CONFIG_NR_DRAM_BANKS   2       /* CS1 may or may not be populated */
 #define PHYS_SDRAM_1           OMAP34XX_SDRC_CS0
 #define PHYS_SDRAM_2           OMAP34XX_SDRC_CS1
 
@@ -208,12 +191,9 @@
 /* Monitor at start of flash */
 #define CONFIG_SYS_MONITOR_BASE                CONFIG_SYS_FLASH_BASE
 
-#define CONFIG_NAND_OMAP_GPMC
-#define SMNAND_ENV_OFFSET              0x260000 /* environment starts here */
-
 #define CONFIG_SYS_ENV_SECT_SIZE       (128 << 10)     /* 128 KiB sector */
-#define CONFIG_ENV_OFFSET              SMNAND_ENV_OFFSET
-#define CONFIG_ENV_ADDR                        SMNAND_ENV_OFFSET
+#define CONFIG_ENV_OFFSET              0x260000
+#define CONFIG_ENV_ADDR                        0x260000
 
 /*-----------------------------------------------------------------------
  * CFI FLASH driver setup
@@ -238,9 +218,6 @@
                                         GENERATED_GBL_DATA_SIZE)
 
 /* Defines for SPL */
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_TEXT_BASE           0x40200800
 #define CONFIG_SPL_MAX_SIZE            (SRAM_SCRATCH_SPACE_ADDR - \
                                         CONFIG_SPL_TEXT_BASE)
 
@@ -255,7 +232,6 @@
 #define CONFIG_SPL_NAND_ECC
 
 /* NAND boot config */
-#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_PAGE_COUNT     64
 #define CONFIG_SYS_NAND_PAGE_SIZE      2048
@@ -276,7 +252,6 @@
  * header. That is 0x800FFFC0--0x80100000 should not be used for any
  * other needs.
  */
-#define CONFIG_SYS_TEXT_BASE           0x80100000
 #define CONFIG_SYS_SPL_MALLOC_START    0x80208000
 #define CONFIG_SYS_SPL_MALLOC_SIZE     0x100000