configs: move CONFIG_SPL_TEXT_BASE to Kconfig

[platform/kernel/u-boot.git] / include / configs / am3517_crane.h

diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index 03b7c26..2c51026 100644 (file)
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * am3517_crane.h - Default configuration for AM3517 CraneBoard.
  *
@@ -6,8 +7,6 @@
  * Based on include/configs/am3517evm.h
  *
  * Copyright (C) 2011 Mistral Solutions pvt Ltd
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __CONFIG_H
@@ -24,8 +23,6 @@
 #define V_OSCK                 26000000        /* Clock output from T2 */
 #define V_SCLK                 (V_OSCK >> 1)
 
-#define CONFIG_MISC_INIT_R
-
 #define CONFIG_CMDLINE_TAG             1       /* enable passing of ATAGs */
 #define CONFIG_SETUP_MEMORY_TAGS       1
 #define CONFIG_INITRD_TAG              1
@@ -58,9 +55,7 @@
 /*
  * select serial console configuration
  */
-#define CONFIG_CONS_INDEX              3
 #define CONFIG_SYS_NS16550_COM3                OMAP34XX_UART3
-#define CONFIG_SERIAL3                 3       /* UART3 on CRANEBOARD */
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
@@ -101,8 +96,6 @@
 /*
  * Board NAND Info.
  */
-#define CONFIG_SYS_NAND_ADDR           NAND_BASE       /* physical address */
-                                                       /* to access nand */
 #define CONFIG_SYS_NAND_BASE           NAND_BASE       /* physical address */
                                                        /* to access */
                                                        /* nand at CS0 */
@@ -180,7 +173,6 @@
 /*-----------------------------------------------------------------------
  * Physical Memory Map
  */
-#define CONFIG_NR_DRAM_BANKS   2       /* CS1 may or may not be populated */
 #define PHYS_SDRAM_1           OMAP34XX_SDRC_CS0
 #define PHYS_SDRAM_2           OMAP34XX_SDRC_CS1
 
@@ -226,7 +218,6 @@
                                         GENERATED_GBL_DATA_SIZE)
 
 /* Defines for SPL */
-#define CONFIG_SPL_TEXT_BASE           0x40200800
 #define CONFIG_SPL_MAX_SIZE            (SRAM_SCRATCH_SPACE_ADDR - \
                                         CONFIG_SPL_TEXT_BASE)